Search Results - "RTL (Computer program language)"

Application of 30m Resolution SRTM DEM in Nepal.

Authors: Jha, Raghunath¹ rnjha@ioe.edu.np

Source: Journal of the Institute of Engineering. 1/1/2018, Vol. 14 Issue 1, p235-240. 6p.

Subjects: Digital elevation models, RTL (Computer program language), Topography, Big data, Aerial photography

Research and Design of RFID Security Authentication Protocol Based on Hash Function.

Authors: ZHANG Feng¹, zhangfeng@126.com

Source: International Journal of Simulation: Systems, Science & Technology; 2016, Vol. 17 Issue 36, p1-9, 9p

Method to Abstract RTL IP Blocks into C++ Code and Enable High-Level Synthesis.

Authors: Bombieri, Nicola Hung-Yi Liu Fummi, Franco et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2013, p1-9, 9p

21st Century Digital Design Tools.

Authors: Dally, William J. Malachowsky, Chris Keckler, Stephen W.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2013, p1-6, 6p

Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms.

Authors: Carven Chan Schwartz-Narbonne, Daniel Sethi, Divjyot et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1226-1232, 7p

System Verification of Concurrent RTL Modules by Compositional Path Predicate Abstraction.

Authors: Urdahl, Joakim Stoffel, Dominik Wedler, Markus et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p334-343, 10p, 9 Diagrams, 1 Chart

A Method to Leverage Pre-Silicon Collateral and Analysis for Post-Silicon Testing and Validation.

Authors: Miller, Gary Bhattarai, Bandana Yu-Chin Hsu et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2011, p575-578, 4p, 1 Diagram, 2 Charts

MAGENTA: Transaction-based Statistical Micro-Architectural Root-Cause Analysis.

Authors: Kamhi, Gila Novakovsky, Alexander Tiemeyer, Andreas et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p639-643, 5p, 2 Diagrams, 1 Chart, 1 Graph

The Day Sherlock Holmes Decided to do EDA.

Authors: Veneris, Andreas Safarpour, Sean

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p631-634, 4p, 6 Diagrams, 1 Chart

Untwist Your Brain -- Efficient Debugging and Diagnosis of Complex Assertions.

Authors: Siegel, Michael Maggiore, Adriana Pichler, Christian

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p644-647, 4p, 2 Black and White Photographs

Exploiting "Architecture for Verification" to Streamline the Verification Process.

Authors: Whipp, Dave, dac09@dave.whipp.name

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p212-215, 4p, 2 Charts

Pre-RTL Formal Verification: An Intel Experience.

Authors: Beers, Robert¹, robert.beers@intel.com

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p806-811, 6p, 1 Chart

Early Formal Verification of Conditional Coverage Points to Identify Intrinsically Hard-to-Verify Logic.

Authors: Ho, C. Richard Theobald, Michael Deneroff, Martin M. et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p268-271, 4p, 2 Diagrams, 2 Charts

SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification.

Authors: Cummings, Clifford E.¹, cliffc@sunburst-design.com

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p231-236, 6p, 1 Diagram, 1 Chart

Using Word-Level Information in Formal Hardware Verification.

Authors: Drechsler, R.¹

Source: Automation & Remote Control. Jun2004, Vol. 65 Issue 6, p963-977. 15p.

Subjects: RTL (Computer program language), Programming languages, Hardware, Tools, Memory, Abstract thought

Implementation of MAC-based RTL module for Inverse DCT in H.264/AVC.

Authors: Park, Ki-Hong Ju, Won-Ki Kim, Yoon-Ho

Source: Multimedia Tools & Applications. Nov2012, Vol. 61 Issue 1, p213-224. 12p.

Subjects: RTL (Computer program language), Electronic data processing, Information storage & retrieval systems, Computer architecture, Array processors, Computer simulation, Video coding

Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation.

Authors: Bag, Joyashree Roy, Subhashis Dutta, P. K. et al.

Source: IETE Journal of Research; Oct2014, Vol. 60 Issue 5, p355-363, 9p

Project verification and construction of superchip tests at the RTL level.

Authors: Zolotorevich, L.¹

Source: Automation & Remote Control; Jan2013, Vol. 74 Issue 1, p113-122, 10p, 8 Diagrams, 5 Charts

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.

Authors: Meloni, Paolo Pomata, Sebastiano Tuveri, Giuseppe et al.

Source: VLSI Design; Jan2012, p1-16, 16p

HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture.

Authors: Thomas, Alexander Rückauer, Michael Becker, Jürgen

Source: International Journal of Reconfigurable Computing; 2012, p1-17, 17p