Search Results - "Adders (Digital electronics)"

Performance Analysis of Different CNTFET Based Full Adder Cells at Nano Scale Regime for Energy Efficient Computing Systems.

Authors: REDDY, DEGA SRINIVASULU PAMULETI, CHALLA DAS, SARI MOHAN et al.

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 3, p255-265, 11p

Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications.

Authors: PAMULETI, CHALLA DAULA, S. M. SHAMSHEER GUNDALA, SRINIVASULU et al.

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 2, p159-173, 15p

Optimized Inexact adder for Approximate Computing Applications.

Authors: G., Narmadha S., Deivasigamani Pugazhendiran, P. et al.

Source: Journal of Engineering Sciences. Mar/Apr2026, Vol. 54 Issue 2, p74-80. 7p.

Optimal IIR Filter Design and FPGA Realization.

Authors: Eddla, Arunjyothi Pappu, V. Y. Jayasree

Source: Engineering, Technology & Applied Science Research; Feb2026, Vol. 16 Issue 1, p31009-31014, 6p

Study on Progress Towards Carbon Nanotube Adder Circuits Capable of Energy Efficient Computing in Integrated Systems.

Authors: DHOLVAN, MOHAN CHAKALI, CHANDRASEKHAR K., NAGENDRAKUMAR et al.

Source: Journal of Active & Passive Electronic Devices; 2026, Vol. 20 Issue 1, p13-25, 13p

Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing.

Authors: CHANDRASEKHAR, CHAKALI DAS, SARI MOHAN JAYACHANDRANATH, S. et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p301-312, 12p

Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.

Authors: PRASAD, T. JAYACHANDRA CHENNAKESAVULU, M. REDDY, BOJJ A. RAMESH et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p283-299, 17p

Study and Implementations of Adder Circuits for Energy and EDP Efficient Computing Systems.

Authors: T., RAMASWAMY RAO, S. P. V. SUBBA BASHA, MOHAMMED MAHABOOB et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p255-269, 15p

An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.

Authors: Dhanasekar, S. Govindaraj, V. Augustine Fletcher, A. S.

Source: International Journal of Electronics. May2026, Vol. 113 Issue 5, p937-957. 21p.

Study and Comparison of 45nm CMOS One-Bit Full Adders Based on Energy-Delay Trade-offs.

Authors: RAMANJANEYULU, N. SEKHAR, P. CHANDRA CHANDRALEKHA, E. et al.

Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 2, p81-97, 17p

High efficiency 16-Bit kogge stone adder design utilizing gate diffusion input technique.

Authors: Rakshitha, A. Shilpa, R. Bindu, S. et al.

Source: AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-6. 6p.

Implementation of Adder Circuits using Majority Functions on Memristor Crossbar.

Authors: Samanta, Pravanjan Das, Partha Pratim Sengupta, Indranil

Source: Journal of Circuits, Systems & Computers. 10/1/2026, Vol. 35 Issue 17, p1-19. 19p.

Subjects: Adders (Digital electronics), Memristors, Threshold logic, Boolean algebra

Low-Power Approximate Adder Design for Image Processing and K-Medians Clustering Applications.

Authors: Gupta, Sanjiv Kumar Dhawan, Amit Tiwari, Manish et al.

Source: IETE Journal of Research. Apr2026, Vol. 72 Issue 4, p902-915. 14p.

Subjects: Adders (Digital electronics), Image processing, Approximation algorithms, Clustering algorithms, Fault tolerance (Engineering), Electronic circuit design, Computer performance

Chip design flow of 6T, 7T, 8T and 9T static random access memory using VLSI development tool.

Authors: Katru, Raju Raghavaiah, B. Salauddin, Md. et al.

Source: AIP Conference Proceedings. 2026, Vol. 3376 Issue 1, p1-8. 8p.

Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.

Authors: Desai, Kushal Agrawal, Yash Rajendran, Sreeja et al.

Source: Microsystem Technologies. Dec2025, Vol. 31 Issue 12, p3835-3846. 12p.

Subjects: Adders (Digital electronics), Static random access memory, Computer architecture, Binary operations, Mechanical efficiency

Design and implementation of a nano-scale digital adder for quantum-based signal processing applications.

Authors: Long, Taotao Du, Honglin

Source: AIP Advances. Feb2026, Vol. 16 Issue 2, p1-9. 9p.

Efficient quantum-dot adder optimisation and analysis for future circuits.

Authors: Chugh, Hemanshi Singh, Sonal

Source: International Journal of Electronics. Sep2025, Vol. 112 Issue 9, p2006-2026. 21p.

Subjects: Adders (Digital electronics), Electronic circuit design, Semiconductor technology, Quantum dot synthesis, Energy dissipation, Quantum dot devices, Digital electronics

An Innovative Approach for Teaching Some Concepts of Digital Design Laboratory Course in 2+2 Program Using a Portable Laboratory Instrumentation.

Authors: Shourabi, Neda Bazyar Owolabi, Oludare Adegbola

Source: Proceedings of the ASEE Annual Conference & Exposition. 2024, p1-9. 9p.

Design the Power Evaluation of a Highly Efficient Low-Complex Adder Implementation Using Inequality Gate by Quantum-Dot Cellular Automata.

Authors: Anjaiah Talamala Patro, Ajit Kumar Pinninti, Kishore

Source: Russian Microelectronics; Dec2025, Vol. 54 Issue 6, p681-689, 9p

Hardware-Described Nanoscale Carry-Save Adder in Quantum-Dot Cellular Automata: An Optimised Design and Evaluation Framework.

Authors: Abdullah-Al-Shafi, Mohammad¹

Source: Chips; Dec2025, Vol. 4 Issue 4, p43, 23p