Search Results - "Array processors"

Optimized fault-tolerant data processing module for high-reliability CNN accelerator.

Authors: Yoon, Sung-Kwang Lee, Seung-Han Jo, Juhyeong et al.

Source: PLoS ONE. 2/27/2026, Vol. 21 Issue 2, p1-17. 17p.

Edge Detection on a 2D-Mesh NoC with Systolic Arrays: From FPGA Validation to GDSII Proof-of-Concept.

Authors: Mascorro-Guardado, Emma Ortega-Cisneros, Susana Ibarra-Villegas, Francisco Javier et al.

Source: Applied Sciences (2076-3417); Jan2026, Vol. 16 Issue 2, p702, 28p

Design of optical–electrical hybrid switching mechanism for array processors.

Authors: Yang, Bowen Huang, Jinyang Shan, Rui et al.

Source: Journal of Computational Methods in Sciences & Engineering (Sage Publications Inc.). Nov2025, Vol. 25 Issue 6, p5357-5374. 18p.

Subjects: Array processors, Optical switching, Data transmission systems, Computer network architectures, Resource allocation, Network performance

A hybrid matrix-vector processor with dynamically reconfigurable dataflow.

Authors: AI, Chenyang ZHAO, Lechuan HUA, Tao et al.

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Nov2025, Vol. 47 Issue 11, p1912-1921. 10p.

Subjects: Matrix multiplications, Array processors, High performance processors, Coprocessors, Adaptive computing systems

Adaptive Steered Frequency–Wavenumber Analysis for High-Frequency Source Localization in Shallow Water.

Authors: Choi, Y. H. Byun, Gihoon Kim, Donghyeon et al.

Source: Sensors (14248220). Apr2025, Vol. 25 Issue 7, p2036. 15p.

Design and Evaluation of Energy‐Efficient Whisper Dot‐Product Kernel Offloading on a CGLA Architecture.

Authors: Ando, Takuto Eto, Yu Takeuchi, Ayumu et al.

Source: Concurrency & Computation: Practice & Experience; Jul2026, Vol. 38 Issue 13, p1-15, 15p

ASFRM: An Array State Self-feedback-Based Self-reconfiguration Mechanism in a Reconfigurable Array Processor.

Authors: Yang, Kun Jiang, Lin Deng, Junyong et al.

Source: Journal of Circuits, Systems & Computers. 9/30/2025, Vol. 34 Issue 14, p1-29. 29p.

Subjects: Array processors, Legal judgments, Scheduling, Encoding, Hardware

Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution.

Authors: Ibrahim, Atef Gebali, Fayez

Source: Applied Sciences (2076-3417); May2024, Vol. 14 Issue 10, p4085, 15p

SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators.

Authors: Pappalardo, Salvatore Bellarmino, Nicolo' Deveautour, Bastien et al.

Source: Journal of Circuits, Systems & Computers; 12/1/2025, Vol. 34 Issue 18, p1-23, 23p

A Symmetric Solar Photovoltaic Inverter to Improve Power Quality Using Digital Pulsewidth Modulation Approach.

Authors: Albert, Johny Renoald Ramasamy, Kannan Joseph Michael Jerard, V. et al.

Source: Wireless Personal Communications; Jun2023, Vol. 130 Issue 3, p2059-2097, 39p

Decoupled Vector Processing Unit: Past, Present, and Future.

Authors: Wang, Ruo-Xi Zhang, Dun-Bo Lang, Qing-Jie et al.

Source: Journal of Computer Science & Technology (10009000); Sep2025, Vol. 40 Issue 5, p1368-1385, 18p

Performance of the ATLAS Level-1 topological trigger in Run 2.

Authors: Aad, G. Abbott, B. Abbott, D. C. et al.

Source: European Physical Journal C -- Particles & Fields. Jan2022, Vol. 82 Issue 1, p1-26. 26p.

Subjects: Field programmable gate arrays, Array processors, Muons, Higgs bosons

DOA estimation algorithm based on spread spectrum sequence in low signal-to-noise ratio.

Authors: Zhou, Feng Zhang, Wenbo Zhang, Baosheng et al.

Source: EURASIP Journal on Wireless Communications & Networking; 7/15/2022, Vol. 2022 Issue 1, p1-17, 17p

Compact Finite Field Multiplication Processor Structure for Cryptographic Algorithms in IoT Devices with Limited Resources.

Authors: Ibrahim, Atef Gebali, Fayez

Source: Sensors (14248220). Mar2022, Vol. 22 Issue 6, p2090. 17p.

Visiting the SARAO Carnarvon.

Source: MNASSA: Monthly Notes of the Astronomical Society of Southern Africa. Jun2021, Vol. 80 Issue 5/6, p117-120. 4p.

Subjects: COVID-19 pandemic, Array processors, Atomic clocks, Radio interference, Focal planes

RVM-LBC: Acceleration of NTT for efficient LBC with custom RISC-V vector–matrix processor.

Authors: Qiu, Yuhang Fan, Zhihua Xue, Jing et al.

Source: Journal of Systems Architecture; Oct2026, Vol. 179, pN.PAG-N.PAG, 1p

SpikeFlow: A hardware–software co-designed systolic array for spiking neural networks.

Authors: Wang, Jianan Shi, Yang Chen, Zhaoyun et al.

Source: Journal of Systems Architecture. Dec2025, Vol. 169, pN.PAG-N.PAG. 1p.

GoibhniUWE: A Lightweight and Modular Container-Based Cyber Range.

Authors: Mills, Alan White, Jonathan Legg, Phil

Source: Journal of Cybersecurity & Privacy; Sep2024, Vol. 4 Issue 3, p615-628, 14p

SWIMM 2.0: Enhanced Smith-Waterman on Intel's Multicore and Manycore Architectures Based on AVX-512 Vector Extensions.

Authors: Rucci, Enzo Giusti, Armando De Garcia Sanchez, Carlos et al.

Source: International Journal of Parallel Programming. Apr2019, Vol. 47 Issue 2, p296-316. 21p.

Subjects: Bioinformatics, Array processors, Intel Corp., SIMD (Computer architecture), Amino acid sequence

窄带物联网信道接收端检测算法的并行化实现.

Alternate Title: Parallel Implementation of Detection Algorithm for Receiver in Narrowband IoT Channel.

Authors: 张新 王瑜 山蕊 et al.

Source: Telecommunication Engineering. 1/28/2020, Vol. 60 Issue 1, p87-91. 5p.