Search Results - "Burger, Doug"

The TRIPS Project.

Authors: Burger, Doug Keckler, Stephen W. McKinley, Kathryn S.

Source: Communications of the ACM. Dec2025, Vol. 68 Issue 12, p90-97. 8p.

Subjects: Central processing units, Federal aid to research, University of Texas at Austin, National Science Foundation (U.S.), Computer science research, High performance computing research, University research, United States. Defense Advanced Research Projects Agency

The Future of Architectural Simulation.

Authors: Burger, Doug Emer, Joel Hoe, James C.

Source: IEEE Micro; May/June 2010, Vol. 30 Issue 3, p8-18, 11p

Mixed-Signal Approximate Computation: A Neural Predictor Case Study.

Authors: St. Amant, Renée Jiménez, Daniel A. Burger, Doug

Source: IEEE Micro; January/February 2009, Vol. 29 Issue 1, p104-115, 12p

Scalable Hardware Memory Disambiguation for High-ILP Processors.

Authors: Sethumadhavan, Simha Desikan, Rajagopalan Burger, Doug

Source: IEEE Micro; Nov/Dec2004, Vol. 24 Issue 6, p118-127, 10p

Speculative Incoherent Cache Protocols.

Authors: Huh, Jaehyuk Burger, Doug Chang, Jichuan

Source: IEEE Micro; Nov/Dec2004, Vol. 24 Issue 6, p104-109, 6p

Scaling to the End of Silicon with EDGE Architectures.

Authors: Burger, Doug Keckler, Stephen W. McKinley, Kathryn S.

Source: Computer; Jul2004, Vol. 37 Issue 7, p44-55, 12p

Billion-transistor Architectures:There and Back Again.

Authors: Burger, Doug Goodman, James R.

Source: Computer; Mar2004, Vol. 37 Issue 3, p22-28, 7p

Nonuniform Cache Architectures for Wire-Delay Dominated on-Chip Caches.

Authors: Kim, Changkyu Burger, Doug Keckler, Stephen W.

Source: IEEE Micro; November/December 2003, Vol. 23 Issue 6, p99-107, 9p

Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements.

Authors: Talla, Deepu John, Lizy Kurian Burger, Doug

Source: IEEE Transactions on Computers; August 2003, Vol. 52 Issue 8, p1015-1031, 17p

Designing a modern memory hierarchy with hardware prefetching.

Authors: Lin, Wei-Fen Reinhardt, Steven K. Burger, Doug

Source: IEEE Transactions on Computers; November 2001, Vol. 50 Issue 11, p1202-1218, 17p

Changing interaction of compiler and architecture.

Authors: Adve, Sarita V. Burger, Doug Eigenmann, Rudolf

Source: Computer; December 1997, Vol. 30, p51-58, 8p

Limited bandwidth to affect processor design.

Authors: Burger, Doug Goodman, James R. Kägi, Alain

Source: IEEE Micro; November/December 1997, Vol. 17, p55-62, 8p

Power Limitations and Dark Silicon Challenge the Future of Multicore.

Authors: Esmaeilzadeh, Hadi Blem, Emily Amant, Renée St. et al.

Source: ACM Transactions on Computer Systems; Aug2012, Vol. 30 Issue 3, p11:1-11:27, 27p

Neural Acceleration for General-Purpose Approximate Programs.

Authors: Esmaeilzadeh, Hadi Sampson, Adrian Ceze, Luis et al.

Source: Communications of the ACM; Jan2015, Vol. 58 Issue 1, p105-115, 11p, 6 Diagrams, 1 Chart, 2 Graphs

Power Challenges May End the Multicore Era.

Authors: Esmaeilzadeh, Hadi Blem, Emily St. Amant, Renée et al.

Source: Communications of the ACM; Feb2013, Vol. 56 Issue 2, p93-102, 10p, 1 Diagram, 2 Charts, 6 Graphs

Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor.

Authors: Fowers, Jeremy Ovtcharov, Kalin Papamichael, Michael K. et al.

Source: IEEE Micro; May-Jun2019, Vol. 39 Issue 3, p20-28, 9p

Configurable Clouds.

Authors: Caulfield, Adrian M. Chung, Eric S. Putnam, Andrew et al.

Source: IEEE Micro; May/Jun2017, Vol. 37 Issue 3, p52-61, 10p

Scaling Power and Performance viaProcessor Composability.

Authors: Govindan, Madhu Saravana Sibi Robatmili, Behnam Li, Dong et al.

Source: IEEE Transactions on Computers; Aug2014, Vol. 63 Issue 8, p2025-2038, 14p

What the Future Holds for Solid-State Memory.

Authors: Strauss, Karin Burger, Doug

Source: Computer (00189162); Jan2014, Vol. 47 Issue 1, p24-31, 8p

Neural Acceleration for General-Purpose Approximate Programs.

Authors: Esmaeilzadeh, Hadi Sampson, Adrian Ceze, Luis et al.

Source: IEEE Micro; May2013, Vol. 33 Issue 3, p16-27, 12p