Search Results - "Chen, Chien-In Henry"

Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection.

Authors: Lee, Yu-Heng George Chen, Chien-In Henry

Source: IEEE Transactions on Instrumentation & Measurement; May 2009, Vol. 58 Issue 5, p1555-1562, 8p

Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip.

Authors: George, Kiran Chen, Chien-In Henry

Source: IEEE Transactions on Instrumentation & Measurement; May 2009, Vol. 58 Issue 5, p1495-1504, 10p

Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test.

Authors: Zhang, Xinhui Chen, Chien-In Henry Chakravarthy, Arvindkumar

Source: IEEE Transactions on Instrumentation & Measurement; March 2008, Vol. 57 Issue 3, p651-663, 13p

Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters.

Authors: Wibbenmeyer, Jason Chen, Chien-In Henry

Source: IEEE Transactions on Instrumentation & Measurement; December 2007, Vol. 56 Issue 6, p2748-2756, 9p

Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS.

Authors: Wang, Mingzhen Chen, Chien-In Henry Radhakrishnan, Shailesh

Source: IEEE Transactions on Instrumentation & Measurement; June 2007, Vol. 56 Issue 3, p1064-1073, 10p

Extension of Two-Signal Spurious-Free Dynamic Range of Wideband Digital Receivers Using Kaiser Window and Compensation Method.

Authors: George, Kiran Chen, Chien-In Henry Tsui, James B. Y.

Source: IEEE Transactions on Microwave Theory & Techniques; April 2007, Vol. 55 Issue 4, p788-794, 7p

Design and Performance Evaluation of a 2.5-GSPS Digital Receiver.

Authors: Chen, Chien-In Henry George, Kiran McCormick, William

Source: IEEE Transactions on Instrumentation & Measurement; June 2005, Vol. 54 Issue 3, p1089-1099, 11p

Configurable Two-Dimensional Linear Feedback Shifter Registers for Parallel and Serial Built-In Self-Test.

Authors: Chen, Chien-In Henry George, Kiran

Source: IEEE Transactions on Instrumentation & Measurement; Aug2004, Vol. 53 Issue 4, p1005-1014, 10p

Comments on “Area-time optimal adder design”.

Authors: Chen, Chien-In Henry Kumar, Anup

Source: IEEE Transactions on Computers; April 1994, Vol. 43, p507-512, 6p

Efficient approaches to low-cost high-fault coverage VLSI BIST designs.

Authors: Chen, Chien-In Henry

Source: IEEE Transactions on Aerospace & Electronic Systems; January 1998, Vol. 34, p63-70, 8p

Data path synthesis in digital electronics. Part I: memory allocation.

Authors: Chen, Chien-In Henry

Source: IEEE Transactions on Aerospace & Electronic Systems; January 1996, Vol. 32, p2-15, 14p

Data path synthesis in digital electronics. Part II: bus synthesis.

Authors: Chen, Chien-In Henry

Source: IEEE Transactions on Aerospace & Electronic Systems; January 1996, Vol. 32, p16-33, 18p

Task allocation and reallocation for fault tolerance in multicomputer systems.

Authors: Chen, Chien-In Henry Cherkassky, Vladimir

Source: IEEE Transactions on Aerospace & Electronic Systems; October 1994, Vol. 30, p1094-1104, 11p

Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor.

Authors: Wang, Yu Chen, Jian Chen, Chien-In Henry

Source: VLSI Design; 5/18/2017, p1-12, 12p

A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement.

Authors: George, Kiran Chen, Chien-In Henry

Source: IEEE Transactions on Instrumentation & Measurement; November 2011, Vol. 60 Issue 12, p3956-3958, 3p

Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection.

Authors: Chen, Jian Chen, Chien-In Henry

Source: VLSI Design; 4/15/2015, Vol. 2015, p1-9, 9p

Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection.

Authors: Wang, Yu Ren, Jianfeng Chen, Chien-In Henry

Source: Integration: The VLSI Journal; Nov2021, Vol. 81, p300-312, 13p

Timing Challenges for Very Deep Sub-Micron (VDSM) IC.

Authors: Ichiang Lin, Hannu Chen, Chien-In Henry

Source: VLSI Design. Nov2002, Vol. 15 Issue 3, p557-562. 6p.

Subjects: Integrated circuits, Integrated circuit interconnections, Very large scale circuit integration, Computer engineering

Timing-Driven-Testable Convergent Tree Adders.

Authors: Huang, Johnnie A. Chen, Chien-In Henry

Source: VLSI Design. Nov2002, Vol. 15 Issue 3, p637-645. 9p.

Subjects: Very large scale circuit integration, Integrated circuits, Integrated circuit interconnections, Cellular automata, Computer engineering

Testability Synthesis for Jumping Carry Adders.

Authors: Chen, Chien-in Henry Wagh, Mahesh

Source: VLSI Design. Mar2002, Vol. 14 Issue 2, p155-169. 15p.

Subjects: Very large scale circuit integration, Methodology, Complementary metal oxide semiconductors, Electrical engineering