Search Results - "Chip scale packaging"

Massively parallel ultrafast random bit generation with a chip-scale laser.

Authors: Kim, Kyungduk Bittner, Stefan Zeng, Yongquan et al.

Source: Science (pre-March 2025). 2/26/2021, Vol. 371 Issue 6532, p948-952. 5p. 4 Diagrams.

Addressing Flux Dip Challenges for 3-D Integrated Large Die, Ultrafine Pitch Interconnect.

Authors: Marsan-Loyer, C. Danovitch, D. Boyer, N.

Source: Journal of Microelectronic & Electronic Packaging. 2017 1st Quarter, Vol. 14 Issue 1, p32-38. 7p.

Subjects: Chip scale packaging, Fine pitch technology, Electronic packaging, Tape-automated bonding, Microelectronics, Magnetic flux

Energy-Aware Modeling of Scaled Heterogeneous Systems.

Authors: Marowka, Ami¹, amimar2@yahoo.com

Source: International Journal of Parallel Programming; Oct2017, Vol. 45 Issue 5, p1026-1045, 20p

Modeling of moisture over-saturation and vapor pressure in die-attach film for stacked-die chip scale packages.

Authors: Chen, Liangbiao Adams, Jeremy Chu, Hsing-Wei et al.

Source: Journal of Materials Science: Materials in Electronics. Jan2016, Vol. 27 Issue 1, p481-488. 8p.

Subjects: Saturation vapor pressure, Chip scale packaging, Transport equation, Thin films, Permeability, Solder & soldering

Laser debonding for ultrathin and stacked fan out packages.

Authors: BRANDL, ELISABETH UHRMANN, THOMAS EIBELHUBER, MARTIN

Source: Solid State Technology; Jul2017, Vol. 60 Issue 5, p12-17, 5p

Using a diffusion wavelet neural network for short-term time series learning in the wafer level chip scale package process.

Authors: Li, Der-Chiang Yeh, Chun-Wu Chen, Chieh-Chih et al.

Source: Journal of Intelligent Manufacturing; Dec2016, Vol. 27 Issue 6, p1261-1272, 12p

In-situ measurement of solder joint strength in board-mounted chip-scale packages using a quantitative laser spallation technique.

Authors: Kim, HyoungIl Tian, Jun Gupta, Vijay

Source: Journal of Adhesion Science & Technology. Apr2013, Vol. 27 Issue 7, p719-730. 12p. 1 Black and White Photograph, 5 Diagrams, 2 Charts, 4 Graphs.

Subjects: Wave mechanics, Chip scale packaging, Solder joints, Simulation methods & models, Industrial lasers, Spallation (Nuclear physics), Strength of materials

Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models.

Authors: Ping Yang Wei Li

Source: International Journal of Numerical Modelling. Jan/Feb2009, Vol. 22 Issue 1, p43-55. 13p. 7 Diagrams, 2 Charts, 8 Graphs.

Subjects: Chip scale packaging, Electronic packaging, Thermal stresses, Finite element method, Computer simulation

FABRICATION OF CHIP SCALE PIEZORESISTIVE PRESSURE SENSORS USING SCREEN-PRINTED GLASS FRIT PACKAGING.

Authors: Iliescu, Ciprian Jianmin Miao, Ciprian Avram, Marioara

Source: International Journal of Computational Engineering Science. Jun2003, Vol. 4 Issue 2, p343-346. 4p.

Subjects: Pressure transducers, Chip scale packaging, Screen process printing, Microelectromechanical systems, Plastic embedment of electronic equipment, Residual stresses

Coupled Integration of CSAC, MIMU, and GNSS for Improved PNT Performance.

Authors: Lin Ma Zheng You Tianyi Liu et al.

Source: Sensors (14248220). May2016, Vol. 16 Issue 5, p682. 19p.

Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications.

Authors: Lau, John Chang, Chris Lee, Ricky et al.

Source: Journal of Electronics Manufacturing. Mar2000, Vol. 10 Issue 1, p79. 9p.

Subjects: Integrated circuits, Chip scale packaging

Steady State and Transient Thermal Analysis of Chip Scale Packages.

Authors: Chambers, Ben Lee, Tien-Yu Tom Blood, William

Source: Journal of Electronics Manufacturing. Jun1999, Vol. 9 Issue 2, p131. 9p.

Subjects: Chip scale packaging, Energy dissipation

Life cycle assessment of integrated circuit packaging technologies.

Authors: Andrae, Anders S. G. Andersen, Otto

Source: International Journal of Life Cycle Assessment. Mar2011, Vol. 16 Issue 3, p258-267. 10p.

Mechanical strength of chip scale package with various underfills under accelerated thermal condition.

Authors: Noh, B. -I. Lee, B. -Y. Jung, S. -B.

Source: Materials Science & Technology. Jul2007, Vol. 23 Issue 7, p828-832. 5p. 4 Diagrams, 2 Charts, 2 Graphs.

Materials Technologies for Thermomechanical Management of Organic Packages.

Authors: Wakharkar, Vijay Matayabas, Chris Lehman, Ed et al.

Source: Intel Technology Journal; Nov2005, Vol. 9 Issue 4, p309-323, 15p

3-D Wire Bondless Switching Cell Using Flip-Chip-Bonded Silicon Carbide Power Devices.

Authors: Seal, Sayan Glover, Michael D. Mantooth, H. Alan

Source: IEEE Transactions on Power Electronics. Oct2018, Vol. 33 Issue 10, p8553-8564. 12p.

Subjects: Chip scale packaging, Electronics packaging, Wide gap semiconductors, Electric properties, Silicon carbide, Three-dimensional display systems

The future role of chip-scale packaging in COTS reliability.

Authors: Gurnett, Keith Adams, Tom

Source: Military & Aerospace Electronics. May2001, Vol. 12 Issue 5, p3. 3p.

Subjects: Chip scale packaging, Electronic systems

Overdriving reliability of chip scale packaged LEDs: Quantitatively analyzing the impact of component.

Authors: Tang, Hongyu Ye, Huaiyu Wong, Cell K.Y. et al.

Source: Microelectronics Reliability. Nov2017, Vol. 78, p197-204. 8p.

Subjects: Light emitting diodes, Chip scale packaging, Quantitative chemical analysis, Electronic color sensors, Dimensional preference

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging.

Authors: Lei Shi Lin Chen David Wei Zhang et al.

Source: Journal of Electronic Packaging. Mar2018, Vol. 140 Issue 1, p1-9. 9p.

Subjects: Wafer level packaging, Chip scale packaging, Thermomechanical treatment, Thermal expansion, Printed circuits

Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio.

Authors: Xiao, Zhiyi Yao, Mingjun Yu, Daquan et al.

Source: Microsystem Technologies. Oct2017, Vol. 23 Issue 10, p4879-4889. 11p.

Subjects: Chip scale packaging, Electroplating, Reliability in engineering, Wafer level packaging, CMOS integrated circuits, Image sensors, Aspect ratio (Images)