Search Results - "Clock distribution networks"

AI Reinvents Chip Design.

Authors: Greengard, Samuel¹, sam@greengard.com

Source: Communications of the ACM; Sep2024, Vol. 67 Issue 9, p16-18, 3p

DESIGN AND PERFORMANCE ANALYSIS OF TERNARY LOGIC BASED ALU USING DOUBLE PRECISION FLOATING POINT.

Authors: Nagarathna R. Aswat, A. R.

Source: Proceedings on Engineering Sciences; 2024, Vol. 6 Issue 3, p903-914, 12p

Post-Routing Latch Optimization for Timing Closure.

Authors: Held, Stephan Schorr, Ulrike

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2014, p29-34, 6p

A Comprehensive Evaluation of Direct and Indirect Network-On- Chip Topologies.

Authors: Baboli, Mehdi Husin, Nasir Shaikh Marsono, Muhammad Nadzir

Source: Proceedings of the International Conference on Industrial Engineering & Operations Management; 2014, p2081-2090, 10p

Design of Zero Skew Clock Tree for CMOS Image Sensor.

Authors: Kansal, Shubhi¹ kansalshubhi@yahoo.com

Source: IUP Journal of Electrical & Electronics Engineering. Oct2013, Vol. 6 Issue 4, p7-12. 6p.

Subjects: Complementary metal oxide semiconductors, Clock distribution networks, Skewness (Probability theory), Electronic systems, Electronic industries

Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.

Authors: MENON, ROHIT P. THORNTON, MITCHELL A.

Source: Journal of Multiple-Valued Logic & Soft Computing. 2014, Vol. 22 Issue 1-2, p21-39. 19p.

Subjects: Clock distribution networks, Many-valued logic, Integrated circuit design, Field programmable gate arrays, Comparative studies, Logic circuits

Clock-Tree Synthesis with Methodology of Reuse in 3D-IC.

Authors: FU-WEI CHEN TINGTING HWANG

Source: ACM Journal on Emerging Technologies in Computing Systems; Apr2014, Vol. 10 Issue 3, p22:1-22:22, 22p

Reliability Improvement of Logic and Clock Paths in Power-Efficient Designs.

Authors: ARASU, SENTHIL NOURANI, MEHRDAD REDDY, VIJAY et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Jan2014, Vol. 10 Issue 1, p3:1-3:23, 23p

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.

Authors: Lerner, Scott Taskin, Baris

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2019, Vol. 27 Issue 1, p1-10. 10p.

Subjects: Mathematical models, Clock distribution networks

DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis.

Authors: Islam, Riadul Fahmy, Hany A. Lin, Ping Y. et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2018, Vol. 26 Issue 10, p2108-2117. 10p.

Subjects: Technology, Clock distribution networks, Electric potential, Methodology, Electrodiffusion

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.

Authors: Chen, Li Chen, Mo Wang, Haibin et al.

Source: Microelectronics Reliability. Aug2018, Vol. 87, p24-32. 9p.

Subjects: Soft errors, Clock distribution networks, Electric inverters, Integrated circuits, Simulation methods & models

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.

Authors: Ewetz, Rickard Koh, Cheng-Kok

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2019, Vol. 38 Issue 6, p1161-1174. 14p.

Subjects: Clock distribution networks, Algorithms, Foundations of arithmetic, Eigenfactor, Clock & watch industry

HCDN: Hybrid-Mode Clock Distribution Networks.

Authors: Islam, Riadul Guthaus, Matthew R.

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Jan2019, Vol. 66 Issue 1, p251-262. 12p.

Subjects: Hybrid power systems, Clock distribution networks, Signal processing

A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators.

Authors: Lin, Yi-Wei Hsu, Shawn S. H.

Source: IEEE Journal of Solid-State Circuits. Nov2017, Vol. 52 Issue 11, p2947-2962. 16p.

Subjects: Clock distribution networks, Complementary metal oxide semiconductors, Bandpass filters

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.

Authors: Sumanth Kumar, Kamineni Reuben, John

Source: Journal of Circuits, Systems & Computers. Nov2016, Vol. 25 Issue 11, p-1. 17p.

Subjects: Clock distribution networks, Integrated circuits, Complementary metal oxide semiconductors, Energy dissipation, Buffer storage (Computer science), Through-silicon via, Algorithms

CMCS: Current-Mode Clock Synthesis.

Authors: Islam, Riadul Guthaus, Matthew R.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Mar2017, Vol. 25 Issue 3, p1054-1062. 9p.

Subjects: Clock distribution networks, Current-mode circuits, Low voltage integrated circuits

Design Methodology for Voltage-Scaled Clock Distribution Networks.

Authors: Sitik, Can Liu, Weicheng Taskin, Baris et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2016, Vol. 24 Issue 10, p3080-3093. 14p.

Subjects: Clock distribution networks, Electric circuit networks, Clock circuits (Electronics), Energy consumption, Energy conservation

Clock buffer polarity assignment under useful skew constraints.

Authors: Joo, Deokjin Kim, Taewhan

Source: Integration: The VLSI Journal. Mar2017, Vol. 57, p52-61. 10p.

Subjects: Clock distribution networks, Signal processing, Scalability, Algorithms, Problem solving

Boundary optimization of buffered clock trees for low power.

Authors: Kim, Joohan Kim, Taewhan

Source: Integration: The VLSI Journal. Jan2017, Vol. 56, p86-95. 10p.

Subjects: Clock distribution networks, Energy consumption, Mathematical optimization, Flip-flop circuits, Automation, Algorithms

Fast clock scheduling and an application to clock tree synthesis.

Authors: Ewetz, Rickard Koh, Cheng-Kok

Source: Integration: The VLSI Journal. Jan2017, Vol. 56, p115-127. 13p.

Subjects: Clock distribution networks, Low voltage integrated circuits, Topology, Electrical engineering, Robust control, Computer science