Search Results - "Computer arithmetic & logic units"

Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector.

Authors: Telagam, Nagarjuna Kandasamy, Nehru

Source: Majlesi Journal of Electrical Engineering. Mar2018, Vol. 12 Issue 1, p103-108. 6p.

Subjects: Computer arithmetic & logic units, Semiconductors, Energy dissipation, Digital electronics, Decoders (Electronics), Central processing units

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.

Authors: Tomar, Geetam Singh George, Marcus Lloyde

Source: Wireless Personal Communications. Feb2018, Vol. 98 Issue 4, p3549-3561. 13p.

Subjects: Computer network architectures, Computer arithmetic & logic units, Multiplying circuits, Field programmable gate arrays, CMOS integrated circuits

Design and Implementation of a 32-Bit ALU: A Review.

Authors: Nandan, Hari Dahiya, Pawan Kumar

Source: IUP Journal of Telecommunications. Feb2019, Vol. 11 Issue 1, p53-63. 11p.

Optimized designs of reversible arithmetic logic unit.

Authors: BOLHASSANI, Ali HAGHPARAST, Majid

Source: Turkish Journal of Electrical Engineering & Computer Sciences. 2017, Vol. 25 Issue 2, p1137-1146. 10p.

Subjects: Computer arithmetic & logic units, Reversible computing, Very large scale circuit integration, Cellular automata, Quantum gates, Quantum computers

Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading.

Authors: Ryotaro Kobayashi Anri Suzuki Hajime Shimada

Source: Journal of Low Power Electronics & Applications; Dec2017, Vol. 7 Issue 4, p32, 15p

Multiple attribute group decision making methods based on trapezoidal fuzzy neutrosophic numbers.

Authors: Ruipu Tan Wende Zhang

Source: Journal of Intelligent & Fuzzy Systems; 2017, Vol. 33 Issue 4, p2547-2564, 18p

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices.

Authors: Verma, Gaurav Kumar, Manish Khare, Vijay et al.

Source: Wireless Personal Communications; Jul2017, Vol. 95 Issue 2, p353-364, 12p

USING XML COMPRESSION FOR WWW COMMUNICATION.

Authors: Müldner, Tomasz Leighton, Gregory Diamond, James

Source: Proceedings of the IADIS International Conference on WWW/Internet; Jan2005, p459-466, 8p, 2 Black and White Photographs, 1 Diagram, 4 Charts

Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.

Authors: Yongsoon Lee Younhee Choi Seok-Bum Ko et al.

Source: EURASIP Journal on Embedded Systems. 1/1/2009, Special section p1-11. 11p. 5 Diagrams, 11 Charts, 5 Graphs.

Subjects: Computer arithmetic & logic units, Artificial neural networks, Floating-point arithmetic, Cost control, Errors

High performance 5 : 2 compressor architectures.

Authors: Menon, R. Radhakrishnan, D.

Source: IEE Proceedings -- Circuits, Devices & Systems. Oct2006, Vol. 153 Issue 5, p447-452. 6p. 8 Diagrams, 3 Charts, 3 Graphs.

Subjects: Compressors -- Design & construction, Computer arithmetic & logic units, Computer circuits, Computers in systems design, Metal oxide semiconductors, Field-effect transistors, Laptop computers, Computer architecture

An Independence Result for Intuitionistic Bounded Arithmetic.

Authors: Moniri, Morteza¹ ezmoniri@ipm.ir

Source: Journal of Logic & Computation. Apr2006, Vol. 16 Issue 2, p199-204. 6p.

Subjects: Arithmetic, Computer arithmetic & logic units, Intuitionistic mathematics, Polynomials, Mathematical formulas, Sentences (Grammar), Mathematical models, Mathematical logic

Algebraic Characterization of Reversible Logic Gates.

Authors: Xiaoyu Song Guowu Yang Perkowski, Marek et al.

Source: Theory of Computing Systems. Mar/Apr2006, Vol. 39 Issue 2, p311-319. 9p. 3 Charts.

Subjects: Computer arithmetic & logic units, Computer logic, Boolean algebra, Quantum computers, Computer circuits, Computer systems

A Simplification Method for AND-EXOR Expressions for Multiple-Output Functions.

Authors: Koda, Norio Sasao, Tsutomu

Source: Systems & Computers in Japan. 8/1/96, Vol. 27 Issue 9, p1-11. 11p.

Subjects: Computer arithmetic & logic units, Algorithms, Computer arithmetic, Logic, Arithmetic, Mathematics

ARRAY AND PIPELINED PROCESSORS.

Authors: Raghavendra, Undaru Agrawal, Dharma P.

Source: Encyclopedia of Electrical & Electronics Engineering; 1999 1st Edition, Vol. 1, p642-647, 6p

A Linear Algorithm for Incremental Digital Display of Circular Arcs.

Authors: Bresenham, Jack

Source: Communications of the ACM. Feb1977, Vol. 20 Issue 2, p100-106. 7p. 1 Diagram, 1 Chart, 3 Graphs.

Subjects: Digital image processing, Computer arithmetic & logic units

One-Pass Compilation of Arithmetic Expressions for a Parallel Processor.

Authors: Stone, Harold S.¹

Source: Communications of the ACM. Apr1967, Vol. 10 Issue 4, p220-223. 4p. 1 Diagram.

Subjects: Parallel processing, Computer arithmetic & logic units, Compilers (Computer programs), Arithmetic, Algorithms, Computer circuits

Design of U-Shaped In-Phase Power Divider Employing Ground-Slotted Technique for Wideband Applications.

Authors: Yusof, Khairul Seman, Norhudah Jamaluddin, Mohd

Source: Wireless Personal Communications; Mar2015, Vol. 81 Issue 1, p359-371, 13p

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA.

Authors: Kumar, Tanesh Pandey, Bishwajeet Das, Teerath et al.

Source: Wireless Personal Communications; Jun2014, Vol. 76 Issue 3, p569-578, 10p

A NOVEL MULTI-WAY POWER DIVIDER DESIGN WITH ARBITRARY COMPLEX TERMINATED IMPEDANCES.

Authors: Jiuchao Li Yuanan Liu Shulan Li et al.

Source: Progress in Electromagnetics Research B; 2013, Vol. 53, p315-331, 17p

8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash.

Source: Radioengineering; Dec2011, Vol. 20 Issue 4, p1-222, 222p