Search Results - "Computer hardware description languages"

Sensorless PMSM Speed Control Using an FPGA-Implemented Unscented Kalman Filter.

Authors: Janiszewski, Dariusz¹

Source: Applied Sciences (2076-3417); Jun2026, Vol. 16 Issue 11, p5429, 24p

Implementation of Midori Cryptographic Algorithm Based on Chisel Language.

Authors: Wang, Jianxin Xu, Huiwen Xiao, Chaoen et al.

Source: Symmetry (20738994). May2026, Vol. 18 Issue 5, p784. 20p.

Designing And Developing An Integrated Hardware And Software System.

Authors: Yachao, Zhang Duraipandi, Oyyappan

Source: Advances in Consumer Research. Jan2026, Vol. 3 Issue 1, p125-133. 9p.

Aspect-Oriented Fault Injection for the Non-Intrusive Resilience Evaluation of Cryptographic Hardware Models.

Authors: Mestiri, Hassen Bouraoui, Mariem Machhout, Mohsen

Source: Engineering, Technology & Applied Science Research; Apr2026, Vol. 16 Issue 2, p34142-34148, 7p

Evaluation of the effects of a hybrid laboratory for learning a hardware description language: Insights into student motivation and academic performance.

Authors: Rodriguez Pinto, Father Alexander Restrepo-Calle, Felipe Ramírez-Echeverry, Jhon Jairo

Source: Research & Practice in Technology Enhanced Learning. 2026, Vol. 21, p1-29. 29p.

Subject Terms: *Learning laboratories, *Academic achievement, *Academic motivation, *Distance education, *Educational technology, Computer hardware description languages, Self-efficacy

硬件描述语言代码缺陷自动调试技术研究综述.

Alternate Title: Review on automated debugging of hardware description language code.

Authors: 徐建军 何枷瑜 吴 江 et al.

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Oct2025, Vol. 47 Issue 10, p1799-1809. 11p.

Subjects: Computer hardware description languages, Debugging, Defect tracking (Computer software development), Integrated circuit verification, Failure analysis

High Clarity, Low Power: Achieving a 43× Speed Boost in Image Defogging Using FPGA Acceleration.

Authors: Pham, Van Khoa Le, Trung Tin

Source: Engineering, Technology & Applied Science Research; Oct2025, Vol. 15 Issue 5, p26376-26382, 7p

A Verilog Programming Learning Assistant System Focused on Basic Verilog with a Guided Learning Method.

Authors: Hsieh, Pin-Chieh Fang, Tzu-Lun Jin, Shaobo et al.

Source: Future Internet. Aug2025, Vol. 17 Issue 8, p333. 34p.

FT-Format: 一种可配置的硬件代码快速格式化工具.

Alternate Title: FT-Format: A configurable hardware code fast formatting tool.

Authors: 陈桂湘 刘胜 郭阳

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Jun2025, Vol. 47 Issue 6, p958-967. 10p.

Subjects: Computer hardware description languages, Integrated circuit design, Maintainability (Engineering), Algorithms, Hardware

Hybrid Wafer Defect Detection and Segmentation Using Verilog-Based Image Preprocessing and Deep Learning Architectures.

Authors: Naik, Bukke Chandrababu Sevagan, S. Kamalakannan, Bharath et al.

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Apr2026, Vol. 51 Issue 8, p10989-11004. 16p.

Subject Terms: *Semiconductor defects, *Computer hardware description languages, *Field programmable gate arrays, *Image enhancement (Imaging systems), *Deep learning

Automatic Generation of Synthesisable Hardware Description Language Code of Multi-Sequence Detector Using Grammatical Evolution.

Authors: Majeed, Bilal Sarma, Rajkumar Youssef, Ayman et al.

Source: Algorithms. Jun2025, Vol. 18 Issue 6, p345. 27p.

Memristor‐Based Logic Circuits: Gate Designs and Cycle‐To‐Cycle Reliability.

Authors: Chandrasekaran, Sridhar Hua, Chen Gao, Shan et al.

Source: IET Circuits, Devices & Systems (Wiley-Blackwell); 6/25/2026, Vol. 2026, p1-9, 9p

Usage of Low‐Cost Auxiliary Moduli for Optimization of Modular Exponentiation Operations.

Authors: Rocha, Paulo Fernandes, Gabriel B. M. Kieslich, Lucas R. et al.

Source: International Journal of Circuit Theory & Applications; Jun2026, Vol. 54 Issue 6, p3082-3095, 14p

Vector-logic models of digital circuits for simulation and rendering.

Authors: Hahanov, Vladimir Chumachenko, Svetlana Litvinova, Eugenia et al.

Source: International Journal of Robotics & Automation (Institute of Advanced Engineering & Science); Jun2026, Vol. 15 Issue 2, p319-330, 12p

Single Cycle Risc-V Processor Using Verilog.

Authors: Hatte, N. M. Kesarkar, V. V. Chirke, S. D. et al.

Source: International Scientific Journal of Engineering & Management; May2026, Vol. 5 Issue 5, p1-4, 4p

Cooperative sensor-display interfaces on a super general-purpose SoC.

Authors: Shinozaki, Hibiki Yamawaki, Akira

Source: Artificial Life & Robotics; May2026, Vol. 31 Issue 2, p378-388, 11p

Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog.

Authors: Shinde, Vaishnavi Karpude, Zeba Kolhe, Pooja et al.

Source: International Scientific Journal of Engineering & Management. Mar2025, Vol. 4 Issue 3, p1-6. 6p.

Design of decryption process for advanced encryption standard algorithm in system-on-chip.

Authors: Prathap, Joseph Anthony Raj, Mrinal Patnaik, Ritu

Source: International Journal of Electrical & Computer Engineering (2088-8708). Dec2024, Vol. 14 Issue 6, p6838-6845. 8p.

Subjects: Advanced Encryption Standard, Computer hardware description languages, Integrated circuit layout, Electronic design automation, Gate array circuits

Design, Verification and Implementation of a Watchdog Timer for Drone Applications.

Authors: Madhushankara, M. Mathew, Ribu Maneesh, M. S. et al.

Source: Journal of Engineering Science & Technology Review. 2024, Vol. 17 Issue 6, p59-65. 7p.

Subjects: Computer hardware description languages, Agricultural drones, Integrated circuits, Voltage, Photography

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories Through Optimal Design of BCH Codes.

Authors: Nabipour, Saeideh Javidan, Javad

Source: Journal of Circuits, Systems & Computers. 11/30/2025, Vol. 34 Issue 17, p1-25. 25p.

Subjects: Computer hardware description languages, Error-correcting codes, Data warehousing, Parallel processing, Transistors