Search Results - "Gate array circuits"

Advanced Security Strategies for Software Vulnerability Protection: A Multi-Scale Detection Model With FPGA-RFID.

Authors: Wang, Yunze Xing, Dan Xu, Man

Source: International Journal of RF Technologies: Research & Applications. Aug2025, Vol. 15 Issue 2, p107-124. 18p.

Subjects: Computer security vulnerabilities, Gate array circuits, Computer software security, Feature extraction, Extraction techniques

面向全同态加密的多项式乘法的加速设计.

Alternate Title: Accelerated design of polynomial multiplication for fully homomorphic encryption.

Authors: 田辉辉 严利民

Source: Journal of Shanghai University / Shanghai Daxue Xuebao. Aug2025, Vol. 31 Issue 4, p735-745. 11p.

P‐14.1: Bit‐plane Compression Model Based on Human Visual Characteristics.

Authors: Qiao, Yang Ji, Yuan Zhang, Yin et al.

Source: SID Symposium Digest of Technical Papers; Jun2025 Supplement 1, Vol. 56, p1680-1683, 4p

P‐1.28: GOA‐AI:Designing the Size of Gate Driver on Array Circuits Using NSGA‐III(II) multi‐objective optimization algorithm framework Combined with Bayesian Optimization.

Authors: Chen, Yanling Hu, Zhenbang Zhou, Xiaoliang et al.

Source: SID Symposium Digest of Technical Papers; Jun2025 Supplement 1, Vol. 56, p792-796, 5p

P‐71: Digital PWM Driving MicroLED Pixel Circuit using a‐ITZO TFTs.

Authors: Kim, Yong-Duck Baek, In Bok Yang, Jong-Heon et al.

Source: SID Symposium Digest of Technical Papers; Jun2025, Vol. 56 Issue 1, p1711-1714, 4p

P‐221: Late‐News Poster: Multi‐Frequency Gate Driver in the Controllable Region for Low Power TFT‐LCD Application.

Authors: Liu, Po-Tsun Zheng, Guang-Ting Chih, Wen-Hui et al.

Source: SID Symposium Digest of Technical Papers; Jun2025, Vol. 56 Issue 1, p1471-1474, 4p

95‐2: Partial Update LCD Based on LTPS Backplane Using a New Gate Driver on Array Combined with Multiplexing Architecture.

Authors: Shao, Chang-Min Lee, Chia-Lun Chen, Ming-Yao et al.

Source: SID Symposium Digest of Technical Papers; Jun2025, Vol. 56 Issue 1, p1317-1320, 4p

Studies and Rejection of Intercrystal Crosstalk on FPGA in a High-Energy Photon-Counting System.

Authors: Chang, Jiahao Zhang, Huaxia Jiang, Shibo et al.

Source: Applied Sciences (2076-3417); Jun2025, Vol. 15 Issue 11, p6050, 13p

Performance Assessment of a GNSS Antenna Array with Digital Beamforming Supported by an FPGA Platform.

Authors: Dores, Gonçalo Dinis, Hugo Baptista, Diogo et al.

Source: Applied Sciences (2076-3417); Jun2025, Vol. 15 Issue 11, p5811, 17p

PLORC: A Pipelined Lossless Reference-Free Compression Architecture for FASTQ Files.

Authors: Zheng, Haori Chen, Jietao Yu, Feng et al.

Source: Applied Sciences (2076-3417); May2025, Vol. 15 Issue 10, p5582, 22p

Hardware-Accelerated Data Readout Platform Using Heterogeneous Computing for DNA Data Storage.

Authors: Gou, Xiaopeng Ge, Qi Guo, Quan et al.

Source: Applied Sciences (2076-3417); May2025, Vol. 15 Issue 9, p5050, 19p

Design Hybrid Architecture to Implement AES Algorithm on FPGA for IoT Applications.

Authors: Mohammed, Nada Qasim Amir, Amiza Salih, Muataz Hammed et al.

Source: Baghdad Science Journal; 2025, Vol. 22 Issue 4, p1379-1392, 14p

A Reconfigurable Framework for Hybrid Quantum–Classical Computing.

Authors: Pratibha Mahmud, Naveed

Source: Algorithms. May2025, Vol. 18 Issue 5, p271. 21p.

Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA.

Authors: Chen, Riguang Chen, Ping Li, Kuinian et al.

Source: Sensors (14248220). May2025, Vol. 25 Issue 9, p2923. 15p.

Hardware-Accelerated Non-Contact System for Sleep Disorder Monitoring and Analysis.

Authors: Sravanthi, Mangali Gunturi, Sravan Kumar Chinnaiah, Mangali Chinna et al.

Source: Sensors (14248220). May2025, Vol. 25 Issue 9, p2747. 17p.

基于三维混沌系统的图像加密及FPGA实现.

Alternate Title: Image encryption and FPGA implementation based on 3D chaotic system.

Authors: 闫少辉 姜嘉伟 崔 宇

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Apr2025, Vol. 47 Issue 4, p686-694. 9p.

Subjects: Image encryption, Gate array circuits, Systems software, Software architecture, Timing circuits

Efficient power optimized very-large-scale integration architecture of proportionate least mean square adaptive filter.

Authors: Lakshmaiah, Gangadharaiah Soralamavu Krishnappa, Narayanappa Chikkajala Ramappa, Poornima Golluchinnappanahalli et al.

Source: International Journal of Electrical & Computer Engineering (2088-8708). Apr2025, Vol. 15 Issue 2, p2513-2522. 10p.

Subjects: Adaptive filters, Gate array circuits, Least squares, Mathematical optimization, Algorithms

On-Satellite Implementation of Real-Time Multi-Object Moving Vehicle Tracking with Complex Moving Backgrounds.

Authors: Yu, Jingyi Wei, Siyuan Wen, Yuxiao et al.

Source: Remote Sensing. Feb2025, Vol. 17 Issue 3, p418. 28p.

Subjects: Affine transformations, Gate array circuits, Relative motion, Information processing, Pixels, Artificial satellite tracking

Optimized Design and Implementation of CRYSTALS‐KYBER Based on MLWE.

Authors: Cheng, Song Chen, Jiansheng Li, Jianyang et al.

Source: Security & Communication Networks; 4/29/2025, Vol. 2025, p1-15, 15p

Transforming Group Codes in Mealy Finite State Machines with Composite State Codes.

Authors: Barkalov, Alexander Titarenko, Larysa Mielcarek, Kamil

Source: Applied Sciences (2076-3417); Apr2025, Vol. 15 Issue 8, p4289, 21p