Search Results - "Integrated memory circuits"

Total Recall.

Authors: FAHEY, JONATHAN

Source: Forbes. 4/30/2001, Vol. 167 Issue 10, p124-128. 3p.

Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell.

Authors: Kavitha, M. Govindaraj, T.

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2016, Vol. 41 Issue 8, p2945-2955. 11p.

Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory

FELINE MICROCHIP: AN EXERCISE IN THE SOCIOLOGY OF DOCUMENTALITY.

Authors: Martignani, Luca¹

Source: Monist. Apr2014, Vol. 97 Issue 2, p236-245. 10p.

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology.

Authors: Limachia, Mitesh Jethabhai Thakker, Rajesh A. Kothari, Nikhil J.

Source: Circuit World. 2018, Vol. 44 Issue 4, p187-194. 8p.

Subjects: Integrated memory circuits, Transistors, Writing, Data, Static relays

Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.

Authors: Prakash, Alok Clarke, Christopher T. Lam, Siew-Kei et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Mar2018, Vol. 26 Issue 3, p445-456. 12p.

Subjects: Systems on a chip, Integrated memory circuits, Embedded computer systems

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack.

Authors: Jin, Minjung Kim, Kangjung Kim, Yoohwan et al.

Source: Microelectronics Reliability. Feb2018, Vol. 81, p201-209. 9p.

Subjects: Static random access memory chips, Integrated memory circuits, Transistors, Gallium nitride, Cyclic loads

Statistical Deviations From the Theoretical Only-SBU Model to Estimate MCU Rates in SRAMs.

Authors: Franco, Francisco J. Clemente, Juan Antonio Baylac, Maud et al.

Source: IEEE Transactions on Nuclear Science. Aug2017, Vol. 64 Issue 8 Part 1, p2152-2160. 9p.

Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory, Programming languages, Electronic data processing

Analysis of SEL on Commercial SRAM Memories and Mixed-Field Characterization of a Latchup Detection Circuit for LEO Space Applications.

Authors: Secondo, R. Alia, R. Garcia Peronnard, P. et al.

Source: IEEE Transactions on Nuclear Science. Aug2017, Vol. 64 Issue 8 Part 1, p2107-2114. 8p.

Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory, Nanosatellites, Artificial satellites

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.

Authors: Gomez, A.F. Lavratti, F. Medeiros, G. et al.

Source: Microelectronics Reliability. Dec2016, Vol. 67, p150-158. 9p.

Subjects: Static random access memory, Integrated memory circuits, Electric testing, Integrated circuits, Phase change memory

Analysis of Functional Oxide based Selectors for Cross-Point Memories.

Authors: Aziz, Ahmedullah Jao, Nicholas Gupta, Sumeet Kumar et al.

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Dec2016, Vol. 63 Issue 12, p2222-2235. 14p.

Subjects: MOS memory circuits, Integrated memory circuits, Magnetic tunnelling

Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization.

Authors: Boley, Jim Beshay, Peter Calhoun, Benton

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dec2015, Vol. 23 Issue 12, p3109-3113. 5p.

Subjects: Static random access memory chips, Integrated memory circuits, Simulation methods & models, Energy consumption, Random access memory

SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase Transition Materials.

Authors: Shen, Zhesheng Srinivasa, Srivatsa Aziz, Ahmedullah et al.

Source: IEEE Transactions on Electron Devices; Feb2019, Vol. 66 Issue 2, p929-937, 9p

Muscle and memory.

Source: Economist. 5/27/2023, Vol. 447 Issue 9348, p55-55. 1/2p.

An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling.

Authors: Yao, Jian Ye, Zuochang Wang, Yan

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jul2015, Vol. 23 Issue 7, p1245-1253. 9p.

Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory, IEEE 802.16 (Standard), Ethernet, IEEE 802 standard

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.

Authors: Chang, Meng-Fan Chen, Ming-Pin Chen, Lai-Fu et al.

Source: IEEE Journal of Solid-State Circuits. Oct2013, Vol. 48 Issue 10, p2558-2569. 12p.

Subjects: Static random access memory chips, Integrated memory circuits, Low voltage integrated circuits, Transistors, Offset reflector antennas, Amplitude variation with offset analysis

A Write-Friendly and Cache-Optimized Hashing Scheme for Non-Volatile Memory Systems.

Authors: Zuo, Pengfei Hua, Yu

Source: IEEE Transactions on Parallel & Distributed Systems; May2018, Vol. 29 Issue 5, p985-998, 14p

Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability.

Authors: Mukhopadhyay, Subhadeep Lee, Yung-Huei Lee, Jen-Hao

Source: Microelectronics Reliability; Feb2018, Vol. 81, p226-231, 6p

PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW.

Authors: TIWARI, NIDHI NEEMA, VAIBHAV RANGRA, KAMAL J. et al.

Source: i-Manager's Journal on Circuits & Systems; Dec2017/Jan2018, Vol. 6 Issue 1, p25-34, 10p

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.

Authors: Zeinali, Behzad Madsen, Jens Kargaard Raghavan, Praveen et al.

Source: International Journal of Circuit Theory & Applications; Nov2017, Vol. 45 Issue 11, p1647-1659, 13p

Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.

Authors: Gulati, Anmol Gupta, Ashutosh Murgai, Shruti et al.

Source: AIP Conference Proceedings. 2016, Vol. 1715 Issue 1, p020002-1-020002-8. 8p. 3 Color Photographs, 6 Diagrams, 5 Charts, 2 Graphs.