Search Results - "Loop tiling (Computer science)"

Optimizing inter-nest data locality in imperfect stencils based on loop blocking.

Authors: Seyfari, Yousef Lotfi, Shahriar Karimpour, Jaber

Source: Journal of Supercomputing. Oct2018, Vol. 74 Issue 10, p5432-5460. 29p.

Subjects: Loop tiling (Computer science), Evolutionary algorithms, High performance computing, Computer memory management, Central processing units, Graphics processing units

Tiling Nussinov's RNA folding loop nest with a space-time approach.

Authors: Palkowski, Marek Bielecki, Wlodzimierz

Source: BMC Bioinformatics. 4/24/2019, Vol. 20 Issue 1, p1-11. 11p. 2 Diagrams, 4 Charts, 2 Graphs.

Bandwidth-Efficient Live Virtual Reality Streaming Scheme for Reducing View Adaptation Delay.

Authors: Jongmin Lee Joohyung Lee Jeongyeon Lim et al.

Source: KSII Transactions on Internet & Information Systems; Jan2019, Vol. 13 Issue 1, p291-304, 14p

Maximizing Communication-Computation Overlap Through Automatic Parallelization and Run-time Tuning of Non-blocking Collective Operations.

Authors: Barigou, Youcef Gabriel, Edgar

Source: International Journal of Parallel Programming. Dec2017, Vol. 45 Issue 6, p1390-1416. 27p.

Subjects: Computer systems, Loop tiling (Computer science), Frequency tuning, Communication, Application program interfaces

Blocking-artifact detection in frequency domain for frame-rate up-conversion.

Authors: Kim, Nam-Uk Lee, Yung-Lyul

Source: Personal & Ubiquitous Computing. Feb2018, Vol. 22 Issue 1, p173-184. 12p. 3 Black and White Photographs, 8 Diagrams, 4 Charts, 3 Graphs.

Subjects: Loop tiling (Computer science), Median filters (Electronics), Digital electric filters, Signal-to-noise ratio, Algorithms

TILING AND SCHEDULING OF THREE-LEVEL PERFECTLY NESTED LOOPS WITH DEPENDENCIES ON HETEROGENEOUS SYSTEMS.

Authors: ZEFREH, EBRAHIM ZAREI LOTFI, SHAHRIAR KARIMPOUR, JABER et al.

Source: Scalable Computing: Practice & Experience. Dec2016, Vol. 17 Issue 4, p331-349. 19p. 8 Charts, 6 Graphs.

Subjects: Loop tiling (Computer science), Heterogeneous computing

State-Based Switching for Optimal Control of Computer Virus Propagation with External Device Blocking.

Authors: Zhu, Qingyi Loke, Seng W. Zhang, Ye

Source: Security & Communication Networks; 5/30/2018, p1-10, 10p

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details.

Authors: Kelefouras, Vasilios¹, kelefouras@ece.upatras.gr

Source: Computing; Sep2017, Vol. 99 Issue 9, p865-888, 24p

DYNAMIC TILE FREE SCHEDULING FOR CODE WITH ACYCLIC INTER-TILE DEPENDENCE GRAPHS.

Authors: BIELECKI, WŁODZIMIERZ SKOTNICKI, PIOTR

Source: Computer Science; 2017, Vol. 18 Issue 2, p195-216, 22p

Proactive Circuit Allocation in Multiplane NoCs.

Authors: Abousamra, Ahmed Jones, Alex K. Melhem, Rami

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2013, p1-10, 10p

TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes.

Authors: Mallik, Arindam Zuber, Paul Tsung-Te Liu et al.

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2013, p1-6, 6p

REGIMap: Register-Aware Application Mapping on Coarse-Grained Reconfigurable Architectures (CGRAs).

Authors: Hamzeh, Mahdi Shrivastava, Aviral Vrudhula, Sarma

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2013, p1-10, 10p

Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis.

Authors: Jason Cong Peng Zhang Yi Zou

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1233-1238, 6p

A Stochastic Jitter Model for Analyzing Digital Timing-Recovery Circuits.

Authors: Burnham, James R. Chih-Kong Ken Yang Hindi, Haitham

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jul2009, p116-121, 6p, 2 Diagrams, 2 Charts, 9 Graphs

EVALUATION OF RANDOMIZED REPLACEMENT POLICIES FOR WEB CACHES.

Authors: González-Cañete, F. J. Sanz-Bustamante, J. Casilari, E. et al.

Source: Proceedings of the IADIS International Conference on WWW/Internet; Jan2007, p227-234, 8p, 1 Chart, 4 Graphs

Counter Examples.

Source: Pipelined Processor Farms; 2001 1st Edition, p189-207, 19p

Minimal Unroll Factor for Code Generation of Software Pipelining.

Authors: Bachir, Mounira Touati, Sid-Ahmed-Ali Brault, Frederic et al.

Source: International Journal of Parallel Programming. Feb2013, Vol. 41 Issue 1, p1-58. 58p. 12 Diagrams, 6 Charts, 9 Graphs.

Subjects: Data pipelining, Loop tiling (Computer science), Parallel processing, Embedded computer systems, Computer software, Ciphers

Proving loop termination: Beyond the traditional method.

Authors: Chen, Tennyson X. Meyer, Martin D.

Source: Journal of Computational Methods in Sciences & Engineering (Sage Publications Inc.). 2009 Supplement 2, Vol. 9, p169-S178. 10p. 1 Chart.

Subjects: Loop tiling (Computer science), Iterative methods (Mathematics), Recursive functions, Recursive programming, Computer memory management

Using Pit to improve security in low-level programs.

Authors: Pedersen, Leif Reza, Hassan

Source: Journal of Supercomputing. Sep2010, Vol. 53 Issue 3, p394-410. 17p. 3 Diagrams.

Subjects: Programming languages, Loop tiling (Computer science), Computer memory management, Computer software

Parallel loop generation and scheduling.

Authors: Lotfi, Shahriar Parsa, Saeed

Source: Journal of Supercomputing. Dec2009, Vol. 50 Issue 3, p289-306. 18p. 13 Diagrams, 1 Chart, 1 Graph.

Subjects: Loop tiling (Computer science), Parallel processing, Computer memory management, Computer science, Electronic data processing