Search Results - "Memory hierarchy (Computer science)"

Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis.

Authors: Jason Cong Peng Zhang Yi Zou

Source: DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1233-1238, 6p

AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.

Authors: Stevens, Jim Tschirhart, Paul Mu-Tien Chang et al.

Source: Intel Technology Journal. 2013, Vol. 17 Issue 1, p184-200. 17p. 3 Diagrams, 1 Chart, 7 Graphs.

Subjects: Computer simulation, Memory hierarchy (Computer science), Cache memory, Dynamic random access memory, Big data, Multicore processors

Performance analysis and optimization of MPI collective operations on multi-core clusters.

Authors: Tu, Bibo Fan, Jianping Zhan, Jianfeng et al.

Source: Journal of Supercomputing. Apr2012, Vol. 60 Issue 1, p141-162. 22p.

Subjects: Multicore processors, Memory hierarchy (Computer science), Mathematical optimization, Cache memory, Computer networks, Algorithms

Region-based parallelization of irregular reductions on explicitly managed memory hierarchies.

Authors: Seonggun Kim Hwansoo Han Kwang-Moo Choe

Source: Journal of Supercomputing. Apr2011, Vol. 56 Issue 1, p25-55. 31p. 9 Charts, 10 Graphs.

Subjects: Memory hierarchy (Computer science), Computer memory management, Computer storage devices, Computer architecture, Embedded computer systems, Technological innovations

Combating I-O bottleneck using prefetching: model, algorithms, and ramifications.

Authors: Verma, Akshat Sen, Sandeep

Source: Journal of Supercomputing. Aug2008, Vol. 45 Issue 2, p205-235. 31p. 2 Diagrams, 1 Chart, 2 Graphs.

Subjects: Memory hierarchy (Computer science), Data transmission systems, Broadband communication systems, Computer storage devices, Algorithms, Computer programming, Bandwidths

Hierarchical Binary Set Partitioning in Cache Memories.

Authors: Zarandi, Hamid Reza Sarbazi-Azad, Hamid

Source: Journal of Supercomputing. Feb2005, Vol. 31 Issue 2, p185-202. 18p.

Subjects: Memory hierarchy (Computer science), Cache memory, Computer storage devices, Computer science, Associative storage

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization.

Authors: Kelefouras, Vasilios Kritikakou, Angeliki Goutis, Costas

Source: Journal of Supercomputing. Apr2014, Vol. 68 Issue 1, p459-487. 29p.

Subjects: Library software, Memory hierarchy (Computer science), Field programmable gate arrays, Computer vision, Computer storage devices

Cache-Oblivious B-Trees.

Authors: Bender, Michael A. Demaine, Erik D. Farach-Colton, Martin

Source: SIAM Journal on Computing. 2005, Vol. 35 Issue 2, p341. 18p.

Subjects: Memory hierarchy (Computer science), Computer storage devices, Data transmission systems, Digital communications, Computer input-output equipment

Hierarchy and the Nature of Information.

Authors: Cottam, Ron Ranson, Willy Vounckx, Roger

Source: Information. 2016, Vol. 7 Issue 1, p1. 10p.

The Design of the PROMIS Compiler—Towards Multi-Level Parallelization.

Authors: Saito, Hideki Stavrakos, Nicholas J. Polychronopoulos, Constantine D. et al.

Source: International Journal of Parallel Programming. Apr2000, Vol. 28 Issue 2, p195-212. 18p.

Subjects: Parallel programming, Memory hierarchy (Computer science), Computer programming, Computer architecture, Computer science

Attack of the Killer Microseconds.

Authors: BARROSO, BY LUIZ MARTY, MIKE PATTERSON, DAVID et al.

Source: Communications of the ACM; Apr2017, Vol. 60 Issue 4, p48-54, 7p, 1 Color Photograph, 3 Charts, 3 Graphs

Asymmetric Memory Hierarchies.

Authors: Williams, John G. Bell, G.

Source: Communications of the ACM. Apr1973, Vol. 16 Issue 4, p213-222. 10p. 4 Diagrams, 1 Chart, 1 Graph.

Subjects: Memory hierarchy (Computer science), Computer storage devices, Computer peripherals, Information storage & retrieval systems, Computer systems, Electronic equipment

Storage Utilization in a Memory Hierarchy When Storage Assignment Is Performed by a Hashing Algorithm.

Authors: Williams, John G. Ashenhurst, R. L.

Source: Communications of the ACM. Mar1971, Vol. 14 Issue 3, p172-175. 4p. 1 Diagram, 3 Graphs.

Subjects: Memory hierarchy (Computer science), Hashing, Algorithms, Computer storage devices, Electronic file management, Computer storage device industry

A Matrix-Matrix Multiplication methodology for single/multi-core architectures using SIMD.

Authors: Kelefouras, Vasilios Kritikakou, Angeliki Goutis, Costas

Source: Journal of Supercomputing; Jun2014, Vol. 68 Issue 3, p1418-1440, 23p

Measurement of the latency parameters of the Multi-BSP model: a multicore benchmarking approach.

Authors: Savadi, Abdorreza Deldari, Hossein

Source: Journal of Supercomputing; Feb2014, Vol. 67 Issue 2, p565-584, 20p

RESOURCE STORAGE MANAGEMENT MODEL FOR ENSURING QUALITY OF SERVICE IN THE CLOUD ARCHIVE SYSTEMS.

Authors: KAPANOWSKI, MARIUSZ SŁOTA, RENATA KITOWSKI, JACEK

Source: Computer Science; 2014, Vol. 15 Issue 1, p3-18, 16p

Infants hierarchically organize memory representations.

Authors: Rosenberg, Rebecca D. Feigenson, Lisa

Source: Developmental Science. Jul2013, Vol. 16 Issue 4, p610-621. 13p. 1 Graph.

Subjects: Short-term memory, Infants, Memory, Memory hierarchy (Computer science), Information organization, Child psychology

On-Chip Caches Built on Multilevel Spin-Transfer Torque RAM Cells and Its Optimizations.

Authors: CHEN, YIRAN WENG-FAI WONG HAI LI et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; May2013, Vol. 9 Issue 2, p16, 22p

Enhancing GPU parallelism in nature-inspired algorithms.

Authors: Cecilia, José Nisbet, Andy Amos, Martyn et al.

Source: Journal of Supercomputing; Mar2013, Vol. 63 Issue 3, p773-789, 17p

Data locality optimization of interference graphs based on polyhedral computations.

Authors: Motallebi, Hassan Parsa, Saeed

Source: Journal of Supercomputing; Sep2012, Vol. 61 Issue 3, p935-965, 31p