Search Results - "Microprocessor design & construction"

深度学习处理器: 人工智能芯片 基础研究之路.

Alternate Title: Deep learning processor: Road to fundamental research on AI chip.

Authors: 陈云霁¹ cyj@ict.ac.cn

Source: Bulletin of the Chinese Academy of Sciences / Chung-kuo ko Hsueh Yuan Yuan Kan. Jun2026, Vol. 41 Issue 6, p1276-1288. 13p.

深度驱动图划分的关键路径延时优化研究.

Alternate Title: Depth-driven graph partitioning for critical path delay optimization.

Authors: 余学雯 陈海燕 黄鹏程

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Apr2026, Vol. 48 Issue 4, p590-598. 9p.

Subjects: Microprocessor design & construction, Directed acyclic graphs, Electronic design automation, Logic circuits, Mathematical optimization

Vektör hızlandırıcılı işlemci tasarımı.

Alternate Title: Processor design with vector accelerator.

Authors: Çakır, Abdülkadir Çakacı, Necati

Source: International Journal of Technological Sciences / Uluslararasi Teknolojik Bilimler Dergisi. Dec2025, Vol. 17 Issue 2, p20-27. 8p.

Research and Implementation of Performance Optimization Methods for RISC-V Level-5 Processors.

Authors: Jin, Zhiwei Hu, Tingpeng Jie, Zhiyi et al.

Source: Applied Sciences (2076-3417); Nov2025, Vol. 15 Issue 21, p11634, 19p

A comprehensive review on implementation analysis of 5-Stage pipelined RISC-V processor.

Authors: Vaishnavi, C. M. Trupti, R. Asuti, Manjunath G. et al.

Source: AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-6. 6p.

Standard cell library based processor design using MGDI technique.

Authors: S, Shankar S, Balamurali P, Sasipriya et al.

Source: International Journal of Electronics. Mar2026, Vol. 113 Issue 3, p465-478. 14p.

Single Cycle Risc-V Processor Using Verilog.

Authors: Hatte, N. M. Kesarkar, V. V. Chirke, S. D. et al.

Source: International Scientific Journal of Engineering & Management; May2026, Vol. 5 Issue 5, p1-4, 4p

A High-Level Synthesis-Driven Framework for Application-Specific Reconfigurable Processor Design in AI Workloads.

Authors: Patel, Pushplata Barhoumia, El Manaa

Source: SCCTS Transactions on Reconfigurable Computing; 2026, Vol. 3 Issue 2, p66-78, 13p

A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors.

Authors: Anitha, A. Rooban, S.

Source: IETE Journal of Research. Dec2025, Vol. 71 Issue 12, p4136-4152. 17p.

Subjects: Microprocessor design & construction, Logic design, Semiconductor technology, Complementary metal oxide semiconductors, Very large scale circuit integration, Microprocessors, Energy consumption

Data-Driven Automated Processor Design.

Authors: Guan, Xiang-Tao Cheng, Shu-Yao Zou, Mo et al.

Source: Journal of Computer Science & Technology (10009000). Jan2026, Vol. 41 Issue 1, p103-113. 11p.

Subjects: Microprocessor design & construction, High performance processors, Parallel processing, Computers

基于软件无线电的 OFDM 通信系统设计与实现. (Chinese)

Authors: 陈 龙 伍 春

Source: Modern Electronic Technology; 2026, Vol. 49 Issue 5, p69-76, 8p

Seamless Integration of Digital Circuits and Assembly Language.

Authors: Yumin Zhang¹

Source: Proceedings of the ASEE Annual Conference & Exposition. 2024, p1-10. 10p.

Capstone Project: CPU Design with Multiplexer.

Authors: Di Mauro, Anthony F. Hawkins, Michael C. Lindsey, Bradley K. et al.

Source: Proceedings of the ASEE Annual Conference & Exposition. 2024, p1-7. 7p.

An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.

Authors: Kumar, Sujeet Ray, Kailash Chandra

Source: International Journal of Parallel, Emergent & Distributed Systems; Jan2026, Vol. 41 Issue 1, p89-103, 15p

[formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.

Authors: Shen, Shidong Chen, Shijie Liu, Yicheng et al.

Source: Journal of Systems Architecture. Jun2026, Vol. 175, pN.PAG-N.PAG. 1p.

Decoupled Vector Processing Unit: Past, Present, and Future.

Authors: Wang, Ruo-Xi Zhang, Dun-Bo Lang, Qing-Jie et al.

Source: Journal of Computer Science & Technology (10009000); Sep2025, Vol. 40 Issue 5, p1368-1385, 18p

Electromigration-Aware Architecture for Modern Microprocessors †.

Authors: Gabbay, Freddy Mendelson, Avi

Source: Journal of Low Power Electronics & Applications; Mar2023, Vol. 13 Issue 1, p7, 18p

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core.

Authors: Barbirotta, Marcello Cheikh, Abdallah Mastrandrea, Antonio et al.

Source: Journal of Low Power Electronics & Applications; Mar2023, Vol. 13 Issue 1, p2, 13p

Building the SHAKTI Microprocessor.

Authors: VEEZHINATHAN, KAMAKOTI¹

Source: Communications of the ACM. Nov2022, Vol. 65 Issue 11, p48-51. 4p. 2 Color Photographs.

Subjects: Microprocessors, Microprocessor design & construction, Microprocessor programming, Microcontrollers, Open source software, Indian Institute of Technology (Chennai, India)

Speeding up the Discrete Cosine Transform Through Custom Operations and Fixed-Point Arithmetic.

Authors: Akçay, Latif Engin, Mustafa Alptekin

Source: Journal of Innovative Science & Engineering (JISE); 2025, Vol. 9 Issue 2, p268-278, 11p