Search Results - "Multiplying circuits"

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.

Authors: Tomar, Geetam Singh George, Marcus Lloyde

Source: Wireless Personal Communications; Feb2018, Vol. 98 Issue 4, p3549-3561, 13p

High-selectivity dual-band filtering power divider using stub-loaded quarter-wavelength resonator.

Authors: Zhao, Xiao-Lan Gao, Li Xu, Jin-Xu et al.

Source: Journal of Electromagnetic Waves & Applications. Nov2015, Vol. 29 Issue 16, p2216-2223. 8p. 1 Color Photograph, 2 Diagrams, 1 Chart, 6 Graphs.

Subjects: Power dividers, Multiplying circuits, Bandpass filters, Wavelengths, Resonators

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves.

Authors: Debapriya Basu Roy Mukhopadhyay, Debdeep Masami Izumi

Source: DAC: Annual ACM/IEEE Design Automation Conference; 2014, p1031-1036, 6p

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.

Authors: Jayashree, H. Thapliyal, Himanshu Arabnia, Hamid et al.

Source: Journal of Supercomputing; Apr2016, Vol. 72 Issue 4, p1477-1493, 17p

A Modified Low Power FFT/IFFT Processor for OFDM Applications.

Authors: Lavanya, S. Jasmin, M.

Source: International Journal of Advanced Research in Computer Science; Mar/Apr2013, Vol. 4 Issue 2, p362-365, 4p

Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer.

Authors: Yildirim, Melih¹, melih.yildirim@tubitak.gov.tr

Source: International Journal of Electronics Letters; Mar2021, Vol. 9 Issue 1, p1-13, 13p

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication.

Authors: Ding, Jinnan Li, Shuguo Gu, Zhen

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Mar2019, Vol. 66 Issue 3, p1003-1016. 14p.

Subjects: Analog multipliers, Multiplying circuits

Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications.

Authors: Akram, Muhammad Hwang, In-Chul

Source: Analog Integrated Circuits & Signal Processing. Oct2017, Vol. 93 Issue 1, p123-136. 14p.

Subjects: Multiplying circuits, Energy management, Systems on a chip, Voltage-controlled oscillators, Phase-locked loops

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications.

Authors: ABDULLAH, DAHLAN¹, dahlan@unimal.ac.id

Source: Journal of VLSI Circuits & Systems (JVCS); 2020, Vol. 2 Issue 1, p1-5, 5p

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction.

Authors: Antelo, Elisardo Montuschi, Paolo Nannarelli, Alberto

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Feb2017, Vol. 64 Issue 2, p409-418. 10p.

Subjects: Analog multipliers, Multiplying circuits

A design of single-ended to differential-ended power divider for X band application.

Authors: Yu, Yongxia Sun, Liguo

Source: Microwave & Optical Technology Letters. Nov2015, Vol. 57 Issue 11, p2669-2673. 5p. 1 Color Photograph, 7 Diagrams, 1 Graph.

Subjects: Dividing circuits, Multiplying circuits, Bandwidths, Spectrum allocation, Digital communications

A Modular Multiplier Implemented With Truncated Multiplication.

Authors: Ding, Jinnan Li, Shuguo

Source: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Nov2018, Vol. 65 Issue 11, p1713-1717, 5p

Efficient hardware implementations of point multiplication for binary Edwards curves.

Authors: Rashidi, Bahram¹, b.rashidi@abru.ac.ir

Source: International Journal of Circuit Theory & Applications; Aug2018, Vol. 46 Issue 8, p1516-1533, 18p

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability.

Authors: Chen, Yuan-Ho¹

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2015, Vol. 23 Issue 1, p203-207. 5p.

Subjects: Multiplying circuits, Digital signal processing, Conditional probability, Complementary metal oxide semiconductors, Balanced truncation

Hybrid-transport point kinetics for initially-critical multiplying systems.

Authors: Picca, Paolo Furfaro, Roberto

Source: Progress in Nuclear Energy. Sep2014, Vol. 76, p232-243. 12p.

Subjects: Multiplying circuits, Model theory, Electric transients, Neutron diffusion, Mathematical models, Computer simulation

Embedded Power and Energy Measurement System Based on an Analog Multiplier.

Authors: Bucci, Giovanni Fiorucci, Edoardo Ciancetta, Fabrizio et al.

Source: IEEE Transactions on Instrumentation & Measurement. Aug2013, Vol. 62 Issue 8, p2248-2257. 10p.

Subjects: Analog multipliers, Multiplying circuits, Energy measurement, Ergometry, Harmonic distortion (Physics)

Design and low speed testing of a four-bit RSFQ multiplier-accumulator.

Authors: Herr, Q.P. Vukovic, N. Mancini, C.A. et al.

Source: IEEE Transactions on Applied Superconductivity. 1997, Vol. 7 Issue 2, p3168-3171. 4p.

Subjects: Multiplying circuits, Digital filters (Mathematics), Josephson junctions, Systolic array circuits, Hypres Inc.

A four-quadrant current multiplier/divider cell with four transistors.

Authors: Elwakil, Ahmed Maundy, Brent Elamien, Mohammed Balla et al.

Source: Analog Integrated Circuits & Signal Processing; Apr2018, Vol. 95 Issue 1, p173-179, 7p

Efficient dual-precision floating-point fused-multiply-add architecture.

Authors: Arunachalam, V. Joseph Raj, Alex Noel Hampannavar, Naveen et al.

Source: Microprocessors & Microsystems; Mar2018, Vol. 57, p23-31, 9p

Efficient ADMM Decoding of LDPC Codes Using Lookup Tables.

Authors: Jiao, Xiaopeng Mu, Jianjun He, Yu-Cheng et al.

Source: IEEE Transactions on Communications; Apr2017, Vol. 65 Issue 4, p1425-1437, 13p