Search Results - "NAND gates"

Energy‐Efficient and Fast IMPLY‐Based Approximate 4:2 Compressor Applying NAND Gates for Image Processing.

Authors: Asgari, Samane Reshadinezhad, Mohammad Reza Fatemieh, Seyed Erfan et al.

Source: Journal of Engineering (2314-4912). 6/18/2026, Vol. 2026, p1-12. 12p.

Subjects: NAND gates, Image processing, Memristors, Logic circuits, Power aware computing

Improving time-domain winner-take-all circuit for neuromorphic computing systems.

Authors: Truong, Son Ngoc Ngo, Tu Tien

Source: International Journal of Electrical & Computer Engineering (2088-8708); Dec2025, Vol. 15 Issue 6, p5173-5182, 10p

Quaternary NAND Gate Simulation Using SWS-FETS and Pseudo Logic Gates.

Authors: Saman, Bander Chandy, J. Jain, F. C.

Source: International Journal of High Speed Electronics & Systems. Mar2026, Vol. 35 Issue 1, p1-12. 12p.

Design and Realization of Novel Dual-Input Logic Gates using Virtual Doped Junctionless Double-Gate TFETs.

Authors: Sharma, Arun Kumar Kumar, Ritik Gopal, Girdhar et al.

Source: Journal of Electronic Materials; Jul2025, Vol. 54 Issue 7, p5901-5917, 17p

Voltage fluctuation of CMOS NAND gate analysed with large deviations theory.

Authors: Yoshino, Daigo Tokura, Yasuhiro

Source: European Physical Journal: Special Topics. Jul2026, Vol. 235 Issue 11, p2819-2824. 6p.

Ultrafast saturable to reverse saturable absorption transition in CoTCPP SURMOF nanofilms and its application to all-optical logic and encryption.

Authors: Saifi, Anam Roy, Sukhdev

Source: Journal of Nonlinear Optical Physics & Materials. Dec2025, Vol. 34 Issue 8, p1-21. 21p.

Subjects: Information technology security, NAND gates, Nanofilms, Laser pulses, Mathematical logic, Logic circuits, Data transmission systems

Inverter and Universal Gates Implementation Using Novel Core Insulator Double Gate (CIDG) MOSFETs.

Authors: Jaiswal, Sushmita Gupta, Santosh Kumar

Source: IETE Journal of Research. Aug2024, Vol. 70 Issue 8, p6940-6949. 10p.

Subjects: NAND gates, Digital electronics, Mathematical logic, Short circuits, Metal oxide semiconductor field-effect transistors

Retention improvement in vertical NAND flash memory using block soft erase scheme.

Authors: Park, Sung-Ho Shin, Dongbeen Oh, Mingyun et al.

Source: Applied Physics Letters; 4/13/2026, Vol. 128 Issue 15, p1-5, 5p

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment.

Authors: Sangam, Sri Lakshmi Sinha, Arun Kumar

Source: International Journal of Electronics. Sep2025, Vol. 112 Issue 9, p1860-1874. 15p.

Subjects: NAND gates, Computer-aided design, Scalability, Electronic circuit design, Logic circuits, Computer performance

Many-Body Effects in a Molecular Quantum NAND Tree.

Authors: Bergfield, Justin P.¹

Source: Quantum Reports; Dec2025, Vol. 7 Issue 4, p45, 16p

Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits.

Authors: Hay, Robert Bhattacharya, Ranajoy Chern, Winston et al.

Source: Applied Sciences (2076-3417); Dec2023, Vol. 13 Issue 23, p12807, 8p

Investigations of all-optical gates based on linear photonic crystals using the PSK technique and beam interference effect.

Authors: Askarian, Asghar Parandin, Fariborz

Source: Electromagnetics. 2023, Vol. 43 Issue 5, p291-308. 18p.

Subjects: Phase shift keying, NAND gates, Logic circuits, Finite differences, Plane wavefronts, Photonic crystals

Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.

Authors: Sharma, Uma Jhamb, Mansi

Source: Circuits, Systems & Signal Processing. May2023, Vol. 42 Issue 5, p2852-2871. 20p.

Subjects: Digital signal processing, NAND gates, Design techniques, Metal oxide semiconductor field-effect transistors, Low voltage systems

Analysis, Simulation and Design of Ternary Logic Circuits Based on CNTFETs in Verilog‐A.

Authors: Marani, Roberto Perri, Anna Gina

Source: International Journal of Numerical Modelling; Sep/Oct2025, Vol. 38 Issue 5, p1-10, 10p

Designing a DNA synchronizer for compact single-rail DNA logic circuits.

Authors: Chenyun Sun Zhikun Zhao Jinyan Zhang et al.

Source: Science Advances. 8/22/2025, Vol. 11 Issue 34, p1-9. 9p.

Design of All-Optical Ternary Inverter and Clocked SR Flip-Flop Based on Polarization Conversion and Rotation in Micro-Ring Resonator.

Authors: Singh, Madan Pal Rakshit, Jayanta Kumar Zoiros, Kyriakos E. et al.

Source: Photonics; Aug2025, Vol. 12 Issue 8, p762, 23p

Realization of high-speed logic functions using heterojunction vertical TFET.

Authors: Ambekar, Vikas Panchore, Meena

Source: Applied Physics A: Materials Science & Processing. Mar2023, Vol. 129 Issue 3, p1-10. 10p. 6 Diagrams, 4 Charts, 7 Graphs.

Subjects: Heterojunctions, NAND gates, Logic, Indium gallium zinc oxide, Germanium, Boolean functions, Threshold voltage

LDML: A Proposal to Reduce Leakage Power in DML Circuits.

Authors: Yadav, Neetika Pandey, Neeta Nand, Deva

Source: Wireless Personal Communications. Mar2023, Vol. 129 Issue 2, p1009-1024. 16p.

Subjects: Leakage, NAND gates, Transistors

Distributed computation with continual population growth.

Authors: Cho, Da-Jung Függer, Matthias Hopper, Corbin et al.

Source: Distributed Computing. Dec2022, Vol. 35 Issue 6, p547-569. 23p.

Subjects: NAND gates, Flow simulations

Design and Optimization of Optical NAND and NOR Gates Using Photonic Crystals and the ML-FOLD Algorithm.

Authors: Mohammadi, Alireza Parandin, Fariborz Karami, Pouya et al.

Source: Photonics; Jun2025, Vol. 12 Issue 6, p576, 14p