Search Results - "Static random access memory chips"

SRAM Has No Chill: Exploiting Power Domain Separation to Steal On-Chip Secrets.

Authors: Mahmod, Jubayer Hicks, Matthew

Source: Communications of the ACM. Aug2025, Vol. 68 Issue 8, p82-90. 9p.

Subjects: Cryptography, Static random access memory chips, Dynamic random access memory, Embedded computer systems, Systems on a chip, Computer security vulnerabilities

Defending Data from SRAM-Based Attacks.

Authors: Saroiu, Stefan¹ (AUTHOR) ssaroiu@microsoft.com

Source: Communications of the ACM. Aug2025, Vol. 68 Issue 8, p81-81. 1p.

A comparative investigation into voltage mode, current mode and charge transfer mode sense amplifiers.

Authors: Singh, Praveen Tiwari, Nidhi Neema, Vaibhav et al.

Source: Microsystem Technologies; Oct2025, Vol. 31 Issue 10, p2827-2836, 10p

On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing.

Authors: Jo, Hyejin Lee, Jaesung Yun, Dai et al.

Source: Integration: The VLSI Journal. Jul2026, Vol. 109, pN.PAG-N.PAG. 1p.

Subjects: Static random access memory chips, On-chip charge pumps, Semiconductor technology

Nintendo Sheds $14 Billion Value After Chip Squeeze Fears Grow.

Authors: Savov, Vlad French, Alice

Source: Bloomberg.com. 12/10/2025, pN.PAG-N.PAG. 1p.

A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time.

Authors: Toyotaka, Kouhei Yakubo, Yuto Furutani, Kazuma et al.

Source: Computing in Science & Engineering. Jan-Mar2024, Vol. 26 Issue 1, p486-494. 9p.

Subjects: Static random access memory chips, Semiconductors

Mehr Bedienkomfort und erweiterte Trace-Unterstützung.

Source: Elektronik Industrie. 3/26/2024, Issue 3, p45-45. 1p.

DIAGNOSTIC TECHNIQUE SELECTION FOR SRAM LOGIC TYPE FAILURES.

Authors: Zhigang Song Safran, Laura

Source: Electronic Device Failure Analysis. May2018, Vol. 20 Issue 2, p18-24. 7p.

Subjects: Static random access memory, Static random access memory chips, Electrical engineering, Failure analysis, Digital electronics

Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power.

Authors: Nayak, Debasish Acharya, Debiprasad Mahapatra, Kamalakanta

Source: Circuits, Systems & Signal Processing. Aug2017, Vol. 36 Issue 8, p3047-3070. 24p.

Subjects: Static random access memory chips, Energy consumption, Short circuits, Electric transformers, Algorithms

Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell.

Authors: Singh, Shalini Akashe, Shyam

Source: Wireless Personal Communications. Sep2017, Vol. 96 Issue 1, p1099-1109. 11p.

Subjects: Static random access memory chips, Energy consumption, Antenna arrays, Data warehousing, Stray currents

A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI.

Authors: Siddiqui, M. Sultan M. Lee, Zhao Chuan Kim, Tony Tae-Hyoung

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2021, Vol. 29 Issue 10, p1707-1719. 13p.

Subjects: Static random access memory, Static random access memory chips

Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation.

Authors: Das, Hritom Haidous, Ali Ahmad Smith, Scott C. et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2021, Vol. 29 Issue 10, p1693-1706. 14p.

Subjects: Static random access memory chips, Memory, Videos

Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology.

Authors: Apostolidis, G. Balobas, D. Konofaos, N.

Source: Journal of Engineering Science & Technology Review. 2016, Vol. 9 Issue 5, p145-149. 5p.

Subjects: Static random access memory chips, Computer architecture, Computer simulation, Comparative studies, Energy dissipation, Energy consumption

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance.

Authors: Reniwal, Bhupendra Vijayvargiya, Vikas Vishvakarma, Santosh et al.

Source: Circuits, Systems & Signal Processing. Sep2016, Vol. 35 Issue 9, p3066-3085. 20p.

Subjects: Static random access memory chips, Field-effect transistors, Simulation methods & models, Electric potential, Integrated memory circuits

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.

Authors: RAJAEI, Ramin ASGARI, Bahar TABANDEH, Mahmoud et al.

Source: Turkish Journal of Electrical Engineering & Computer Sciences. 2017, Vol. 25 Issue 2, p1035-1047. 13p.

Subjects: Static random access memory chips, Complementary metal oxide semiconductors, Radiation, Soft errors, Single event effects

Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell.

Authors: Kavitha, M. Govindaraj, T.

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2016, Vol. 41 Issue 8, p2945-2955. 11p.

Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory

SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.

Authors: Gao, Lan Wang, Rui Xu, Yunlong et al.

Source: Journal of Supercomputing; Jul2018, Vol. 74 Issue 7, p3388-3414, 27p

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications.

Authors: Singh, Pooran Vishvakarma, Santosh Kumar

Source: Journal of Low Power Electronics & Applications; Sep2017, Vol. 7 Issue 3, p24, 22p

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability.

Authors: Mittal, Sparsh Rujia Wang Vetter, Jeffrey

Source: Journal of Low Power Electronics & Applications; Sep2017, Vol. 7 Issue 3, p23, 24p

A 28-nm 32 Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques.

Authors: KUMAR, Satyendra SAHA, Kaushik GUPTA, Hariom

Source: Radioengineering; Sep2017, Vol. 26 Issue 3, p772-780, 9p