Search Results - "Systems on a chip--Testing"

Compact CMOS-Compatible Power Amplifier with Enhanced Linearity for IoT Transmitters.

Authors: Bara, M. F. Snousi, Haitham M.

Source: National Journal of RF Circuits & Wireless Systems; 2026, Vol. 3 Issue 1, p16-23, 8p

A neuro-inspired visual tracking method based on programmable system-on-chip platform.

Authors: Yang, Shufan Wong-Lin, KongFatt Andrew, James et al.

Source: Neural Computing & Applications. Nov2018, Vol. 30 Issue 9, p2697-2708. 12p.

Subjects: Systems on a chip testing, Image processing, Object tracking (Computer vision), Artificial neural networks, Iterative methods (Mathematics)

An autonomous, highly portable NMR spectrometer based on a low-cost System-on-Chip (SoC).

Authors: Ariando, David Chen, Cheng Greer, Mason et al.

Source: Journal of Magnetic Resonance. Feb2019, Vol. 299, p74-92. 19p.

Subjects: NMR spectrometers, Systems on a chip testing, Field programmable gate arrays, Signal-to-noise ratio, Permanent magnets

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.

Authors: Subramanyan, Pramod Huang, Bo-Yuan Vizel, Yakir et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Aug2018, Vol. 37 Issue 8, p1692-1705. 14p.

Subjects: Systems on a chip, Systems on a chip testing, Hardware, Cryptography, Python programming language

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.

Authors: Liu, Yongpan Su, Fang Yang, Yixiong et al.

Source: IEEE Journal of Solid-State Circuits. Mar2019, Vol. 54 Issue 3, p885-895. 11p.

Subjects: Ferroelectric capacitors, Systems on a chip testing, Computer systems

Picocom introduces industry's first system-on-chip for 5G small cell Open RAN radio units.

Source: Telecom Industry Snapshot. 11/17/2023, p18-19. 2p.

Thermal Aware Test Scheduling for NTV Circuit.

Authors: Lim, Jaeil Oh, Hyunggoy Kim, Heetae et al.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Apr2018, Vol. 37 Issue 4, p906-910. 5p.

Subjects: Threshold voltage measurement, Systems on a chip testing, Energy consumption, Electric circuits, Simulation methods & models

Fast 3D Integrated Circuit Placement Methodology using Merging Technique.

Authors: Sabbavarapu, Srinivas Acharyya, Amit Balasubramanian, P. et al.

Source: Defence Science Journal; May2019, Vol. 69 Issue 3, p217-222, 6p

Thermal Aware SOC Testing by Introducing Cooling Period.

Authors: Sarkar, Trupa Chakraborty, Shrabanti Paul, Bikram et al.

Source: IETE Technical Review. Mar2017, Vol. 34 Issue 2, p113-121. 9p.

Subjects: Systems on a chip testing, Cooling, Thermal comfort, Genetic algorithms, Temperature measurements

Design for Testability of Sleep Convention Logic.

Authors: Parsan, Farhad A. Smith, Scott C. Al-Assadi, Waleed K.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Feb2016, Vol. 24 Issue 2, p743-753. 11p.

Subjects: Systems on a chip, Systems on a chip testing, Logic circuits, Industrial costs, Fault tolerance (Engineering)

Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains.

Authors: Arslan, Baris Orailoglu, Alex

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jan2016, Vol. 35 Issue 1, p141-154. 14p.

Subjects: Systems on a chip testing, Delay differential equations, Radio frequency, Mathematical optimization, Algorithms

Towards the development of human immune-system-on-a-chip platforms.

Authors: Polini, Alessandro del Mercato, Loretta L. Barra, Adriano et al.

Source: Drug Discovery Today. Feb2019, Vol. 24 Issue 2, p517-525. 9p.

Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC.

Authors: Appello, Davide Bernardi, Paolo Bugeja, Conrad et al.

Source: Journal of Electronic Testing. Feb2018, Vol. 34 Issue 1, p43-52. 10p.

System-on-Chip Test Architectures : Nanometer Design for Testability

Authors: Laung-Terng Wang Charles E. Stroud Nur A. Touba

Resource Type: eBook.

Subjects: Integrated circuits--Very large scale integration--Design, Integrated circuits--Very large scale integration--Testing, Systems on a chip--Testing

Categories: TECHNOLOGY & ENGINEERING / Industrial Design / Product, TECHNOLOGY & ENGINEERING / Electrical

Verification Techniques for System-Level Design

Authors: Masahiro Fujita Indradeep Ghosh Mukul Prasad

Resource Type: eBook.

Subjects: Formal methods (Computer science), Integrated circuits--Verification, Systems on a chip--Testing

Categories: COMPUTERS / Computer Architecture, TECHNOLOGY & ENGINEERING / Industrial Design / Product

Power, Performance, and Area Optimization of SoCET's AFTx07+ Chip.

Authors: Mukadam, Ammar

Source: Journal of Purdue Undergraduate Research. 2025, Vol. 15 Issue 1, p115-116. 2p.

Inference runtime of a neural network to detect atrial fibrillation on customized RISC-V-based hardware.

Source: Current Directions in Biomedical Engineering; Aug2022, Vol. 8 Issue 2, p703-706, 4p

Advanced Production Testing of RF, SoC, and SiP Devices

Authors: Kelly, Joe Engelhart, Michael

Resource Type: eBook.

Subjects: Systems on a chip--Testing

Categories: TECHNOLOGY & ENGINEERING / Electronics / Circuits / General, TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated

Dynamic Self-Repair Architectures for Defective Through-silicon Vias.

Authors: Joon-Sung Yang Tae Hee Han Kobla, Darshan et al.

Source: ETRI Journal; Apr2014, Vol. 36 Issue 2, p301-308, 8p

A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture.

Authors: Dongkwan Han Yong Lee Sungho Kang

Source: ETRI Journal; Apr2014, Vol. 36 Issue 2, p293-300, 8p