Search Results - "Systolic array circuits"

ASIC Implementation of Hardware Efficient DTCWT Architecture for Intra Prediction HEVC Coding in Complex Wavelet.

Authors: Madhurima, V. Padmapriya, K.

Source: Ingénierie des Systèmes d'Information. Apr2022, Vol. 27 Issue 2, p193-204. 12p.

FPGA-Based Parallel Implementation of Morphological Operators for 2D Gray-Level Images.

Authors: Mukherjee, Debasish Mukhopadhyay, Susanta Biswas, G.

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2017, Vol. 42 Issue 8, p3191-3206. 16p.

Subjects: Systolic array circuits, Parallel algorithms

Systematic Mapping of Uniform Recurrent Equation onto Linear Systolic Array.

Authors: Mosleh, Mohammad Kheyrandish, Mohammad Setayeshi, Saeid et al.

Source: International MultiConference of Engineers & Computer Scientists 2007 (Volume 1). 2007, p600-604. 5p. 3 Diagrams, 2 Charts, 2 Graphs.

Subjects: Systolic array circuits, Point mappings (Mathematics), Linear systems, Mathematical mappings, Functional differential equations

WAFER-SCALE INTEGRATION.

Authors: Razzaghi, Mohsen Nazabzadeh, Jalal

Source: Encyclopedia of Electrical & Electronics Engineering. 1999 1st Edition, Vol. 23, p413-429. 17p.

Subjects: Wafer-scale integration of circuits, Systolic array circuits, Microelectronics, Reduced instruction set computers, Semiconductors, Digital electronics

High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT.

Authors: Usha Bhanu, N. Chilambuchelvan, A.

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Aug2014, Vol. 39 Issue 8, p6125-6135. 11p.

Subjects: Discrete wavelet transforms, Systolic array circuits, Field programmable gate arrays, Computer engineering, Computer science

Parametric minimum hardware QR-factoriser architecture for V-BLAST detection.

Authors: Sobhanmanesh, F. Nooshabadi, S.

Source: IEE Proceedings -- Circuits, Devices & Systems. Oct2006, Vol. 153 Issue 5, p433-441. 9p. 9 Diagrams, 6 Charts, 6 Graphs.

Subjects: Wireless communications, Systolic array circuits, Transmitting antennas, Signal processing, Array processors, Critical path analysis, Least squares

Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform.

Authors: Nayak, S. S.¹

Source: IEE Proceedings -- Circuits, Devices & Systems. Feb2005, Vol. 152 Issue 1, p25-32. 8p.

Subjects: Systolic array circuits, Wavelets (Mathematics), Algorithms, Computer arithmetic

A CUBIC SYSTOLIC ARRAY AND ITS PROPERTIES.

Authors: Ishihara, M. Tanaka, M. Kuriyama, K.

Source: International Journal of Computers & Applications. 2008, Vol. 30 Issue 3, p173-182. 10p.

Subjects: Systolic array circuits, High performance processors, Cellular automata, Artificial neural networks, Computer storage devices

Synthesis of space optimal systolic arrays for band matrix-vector multiplication.

Authors: Milovanović, E. Bekakos, M. Milovanović, I.

Source: Journal of Supercomputing. Sep2009, Vol. 49 Issue 3, p269-290. 22p. 10 Diagrams, 2 Charts, 2 Graphs.

Subjects: Systolic array circuits, Matrices (Mathematics), Mathematical transformations, Graphic methods, Integrated circuits

Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.

Authors: Milovanović, E. Milovanović, I. Bekakos, M. et al.

Source: Journal of Supercomputing. Apr2007, Vol. 40 Issue 1, p49-66. 18p. 6 Diagrams, 6 Charts, 3 Graphs.

Subjects: Systolic array circuits, Directed graphs, Computer simulation, Linear electric circuits, Algorithms, Vector processing (Computer science), Computer software, Computer engineering, Computer science

A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method.

Authors: Karra, M. Bekakos, M.

Source: Journal of Supercomputing. Sep2006, Vol. 37 Issue 3, p319-331. 13p. 1 Color Photograph, 8 Diagrams, 2 Charts.

Subjects: Systolic array circuits, Very large scale circuit integration, Field programmable gate arrays, Integrated circuits, Very high speed integrated circuits, Programmable logic devices, Gate array circuits, Factorization of operators, Prototypes

Propagation characteristics of microstrip lines with 2D defected ground structures.

Authors: Hai-Wen Liu Xiao-Wei Sun Zheng-Fan Li et al.

Source: International Journal of RF & Microwave Computer-Aided Engineering. May2006, Vol. 16 Issue 3, p280-286. 7p. 2 Diagrams, 1 Chart, 7 Graphs.

Subjects: Strip transmission lines, Systolic array circuits, Simulation methods & models, Measurement, Microwaves

EFFICIENT SYSTOLIC SINUSOIDAL SEQUENCE GENERATION.

Authors: Alwan, Nuha A. S.¹ n.alwan@ieee.org

Source: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Apr2008, Vol. 33 Issue 1B, p179-186. 8p. 3 Diagrams, 1 Chart.

Subjects: Systolic array circuits, Evolutionary computation, Computational complexity, Stiff computation (Differential equations), Mathematics in electrical engineering, Signal processing

Lipofundin®MCT/LCT 20% increase left ventricular systolic pressure in an ex vivo rat heart model via increase of intracellular calcium level.

Authors: Jiyoung Park Yeon A Kim Jeong Yeol Han et al.

Source: Korean Journal of Anesthesiology. Feb2016, Vol. 69 Issue 1, p57-62. 6p.

Design and Evaluation of Wafer Transfer System for LSI Production.

Authors: Sakano, Susumu Kuroda, Hisao Asakawa, Makoto

Source: Electronics & Communications in Japan, Part 2: Electronics. Aug87, Vol. 70 Issue 8, p30-42. 13p.

Subjects: Wafer-scale integration of circuits, Systolic array circuits, Very large scale circuit integration, Integrated circuits, Electronic circuits, Electronic systems

Multipath Suppression Performance of an Adaptive Array Antenna with a Systolic Array Processor.

Authors: Ohmiya, Manabu Kawabata, Tatsuya Ogawa, Yasutaka et al.

Source: Electronics & Communications in Japan, Part 1: Communications. Nov93, Vol. 76 Issue 11, p95-104. 10p.

Subjects: Systolic array circuits, Radio (Medium), Data pipelining, Electronics

Geographic Terms: Japan

A Hypercube Design on Wafer-Scale Integration.

Authors: Ito, Hideo Suzuki, Nobuyuki

Source: Systems & Computers in Japan. 3/1/91, Vol. 22 Issue 4, p29-40. 12p.

Subjects: Wafer-scale integration of circuits, Systolic array circuits, Hypercube networks (Computer networks), Parallel processing, Computer architecture, Computer systems

A Fast Processor for 3-D Device Simulation Using Systolic Arrays.

Authors: Naritomi, Takashi Aso, Hirotomo Kimura, Masayuki

Source: Systems & Computers in Japan. 1/1/91, Vol. 22 Issue 1, p39-48. 10p.

Subjects: Systolic array circuits, Wafer-scale integration of circuits, Very large scale circuit integration, Semiconductors, Parallel processing, Electronic data processing

A Prolog Machine Based on VLSI Algorithms.

Authors: Shobatake, Yasuro Aiao, Rideo

Source: Systems & Computers in Japan. Feb89, Vol. 20 Issue 2, p15-24. 10p.

Subjects: Very large scale circuit integration, Systolic array circuits, Algorithms, Electronics, Transputers

Formal Description of Systolic Algorithms and an Analysis of the Information Flow.

Authors: Aso, Hirotome Yasuyoshi Inagaki

Source: Systems & Computers in Japan. Jun88, Vol. 19 Issue 6, p14-24. 11p.

Subjects: Systolic array circuits, Integrated circuits, Hardware, Algorithms, Mathematical functions, Electronic data processing