Search Results - "Taskin, Baris"

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking.

Authors: Taskin, Baris Hong, Bo

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; December 2008, Vol. 16 Issue 12, p1648-1656, 9p

Delay Insertion Method in Clock Skew Scheduling.

Authors: Taskin, Baris Kourtev, Ivan S.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; April 2006, Vol. 25 Issue 4, p651-663, 13p

Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits.

Authors: Taskin, Baris Kourtev, Ivan S.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; January 2004, Vol. 12 Issue 1, p12-27, 16p

FinFET-Based Low-Swing Clocking.

Authors: SITIK, CAN SALMAN, EMRE FILIPPINI, LEO et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; Aug2015, Vol. 12 Issue 2, p13:1-13:20, 20p

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion.

Authors: Ganguly, Amlan Abadal, Sergi Thakkar, Ishan et al.

Source: IEEE Micro; May/Jun2022, Vol. 42 Issue 3, p40-49, 10p

A Shift-Register-Based QCA Memory Architecture.

Authors: TASKIN, BARIS CHIU, ANDY SALKIND, JONATHAN et al.

Source: ACM Journal on Emerging Technologies in Computing Systems; 2009, Vol. 5 Issue 1, p1-18, 18p, 8 Black and White Photographs, 9 Diagrams, 2 Charts

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.

Authors: Kuttappa, Ragh Taskin, Baris Lerner, Scott et al.

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Apr2021, Vol. 68 Issue 4, p1636-1645. 10p.

Subjects: Synchronization, Silicon

Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.

Authors: Lerner, Scott Taskin, Baris

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2019, Vol. 27 Issue 1, p1-10. 10p.

Subjects: Mathematical models, Clock distribution networks

TSV-based antenna for on-chip wireless communication.

Authors: Pano, Vasil Tekin, Ibrahim Yuqiao Liu et al.

Source: IET Microwaves, Antennas & Propagation (Wiley-Blackwell); 2020, Vol. 14 Issue 4, p302-307, 6p

The Adiabatically Driven StrongARM Comparator.

Authors: Filippini, Leo Taskin, Baris

Source: IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Dec2019, Vol. 66 Issue 12, p1957-1961, 5p

Design and fabrication of two-port three-beam switched beam antenna array for 60 GHz communication.

Authors: Yuqiao Liu Bshara, Oday Tekin, Ibrahim et al.

Source: IET Microwaves, Antennas & Propagation (Wiley-Blackwell); 2019, Vol. 13 Issue 9, p1438-1442, 5p

SLECTS: Slew-Driven Clock Tree Synthesis.

Authors: Liu, Weicheng Sitik, Can Salman, Emre et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Apr2019, Vol. 27 Issue 4, p864-874, 11p

Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors.

Authors: Lerner, Scott Yilmaz, Isikcan Taskin, Baris

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Mar2019, Vol. 27 Issue 3, p700-710, 11p

Vertical Arbitration-Free 3-D NoCs.

Authors: More, Ankit Pano, Vasil Taskin, Baris

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Sep2018, Vol. 37 Issue 9, p1853-1866, 14p

FOPAC: Flexible On-Chip Power and Clock.

Authors: Kuttappa, Ragh Kose, Selcuk Taskin, Baris

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Dec2019, Vol. 66 Issue 12, p4628-4636, 9p

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design.

Authors: Teng, Ying Taskin, Baris

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Nov2015, Vol. 23 Issue 11, p2519-2530. 12p.

Subjects: Clock distribution networks, Electric circuit networks, Clock circuits (Electronics), Time-varying networks, Electric networks

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer.

Authors: Kuttappa, Ragh Balaji, Adarsha Pano, Vasil et al.

Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Jul2019, Vol. 66 Issue 7, p2685-2698, 14p

Design Methodology for Voltage-Scaled Clock Distribution Networks.

Authors: Sitik, Can Liu, Weicheng Taskin, Baris et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2016, Vol. 24 Issue 10, p3080-3093, 14p

STATISTICAL TIMING ANALYSIS OF THE CLOCK PERIOD IMPROVEMENT THROUGH CLOCK SKEW SCHEDULING.

Authors: KURTAS, SHANNON M. TASKIN, BARIS

Source: Journal of Circuits, Systems & Computers. Aug2011, Vol. 20 Issue 5, p881-898. 18p. 6 Diagrams, 2 Charts.

Subjects: Time-sharing computer systems, Statistics, Distribution (Probability theory), Registers (Computers), Integrated circuits, Mathematical models, Computer scheduling

MULTI-PHASE ROTARY CLOCK SYNCHRONIZATION OF LEVEL-SENSITIVE CIRCUITS.

Authors: TASKIN, BARIS KOURTEV, IVAN

Source: Journal of Circuits, Systems & Computers. Aug2009, Vol. 18 Issue 5, p899-908. 10p. 3 Diagrams, 2 Charts, 1 Graph.

Subjects: Parallel resonant circuits, Electric circuits, Frequencies of oscillating systems, Electronics, Electric equipment