Search Results - "Verilog (Computer hardware description language)"

A Low-Power DWS-CNN-Based Downsampling Approach for Odor Identification Using Herbal and Organic Datasets.

Authors: Aldi, Akshata K. Raibagkar, R. L.

Source: Engineering, Technology & Applied Science Research; Jun2026, Vol. 16 Issue 3, p36305-36311, 7p

OpenPCIe: An Open-Source PCIe Controller.

Authors: Idris, Somoye Jovel, David Mannan, Lamia

Source: Applied Sciences (2076-3417); Apr2026, Vol. 16 Issue 7, p3409, 19p

FPGA-based Implementation of Dark Channel Prior for Image Dehazing.

Authors: Agrawal, Anita B. K., Richa Jain, Karun et al.

Source: Grenze International Journal of Engineering & Technology (GIJET); Jan2026, Vol. 12 Issue Part2, p1996-2000, 5p

Energy Efficient Approximate Multiplier for Error Resilient Applications.

Authors: Rasoju, Veerabadra Chary Anil Kumar, Uppugunduru Jonnalagadda, Aditya Anirudh et al.

Source: Journal of Circuits, Systems & Computers. 7/30/2026, Vol. 35 Issue 12, p1-16. 16p.

Subjects: Logic design, Verilog (Computer hardware description language), Computer engineering, Fault tolerance (Engineering), Binary operations

A Verilog Programming Learning Assistant System Focused on Basic Verilog with a Guided Learning Method.

Authors: Hsieh, Pin-Chieh Fang, Tzu-Lun Jin, Shaobo et al.

Source: Future Internet. Aug2025, Vol. 17 Issue 8, p333. 34p.

Implementation of Serial Peripheral Interface Slave Device Based on Uncommitted Logic Arrays.

Authors: Sinyukin, Alexander Denisenko, Mark Isaeva, Alina et al.

Source: Serbian Journal of Electrical Engineering. Feb2025, Vol. 22 Issue 1, p1-16. 16p.

Subjects: Verilog (Computer hardware description language), Programmable logic devices, Logic circuits, Digital technology, Integrated circuits

Reduction of Interference Terms in Wigner Ville Distribution using Machine Learning.

Authors: Satyanarayana, S. V. V. Murali Krishna, B. Satyanarayana, P. V. V. et al.

Source: Circuits, Systems & Signal Processing. Mar2025, Vol. 44 Issue 3, p2041-2072. 32p.

Subjects: Verilog (Computer hardware description language), Field programmable gate arrays, Wigner distribution, Power density, Machine learning

Improved Verilog‐A Based Artificial Neural Network Modeling Applied to GaN HEMTs.

Authors: Jarndal, Anwar Ansari, Md Hasnain Dautov, Kassen et al.

Source: Advanced Theory & Simulations. Feb2025, Vol. 8 Issue 2, p1-11. 11p.

IoT based Performance Improvement of Single Instruction Multiple Data (SIMD) Processor Array for Wireless Sensor Networks Application.

Authors: VELLIANGIRI, A. KALIMUTHU, VINOTH KUMAR BALAJI, C. G. et al.

Source: Technical Gazette / Tehnički Vjesnik. 2025, Vol. 32 Issue 1, p66-71. 6p.

Subjects: SIMD (Computer architecture), Verilog (Computer hardware description language), Field programmable gate arrays, Wireless sensor networks, Array processors

FPGA based Hardware Implementation of k-Nearest Neighbors(k-NN) Algorithm using the Manhattan Distance Metric for Binary Classification Tasks.

Authors: Arumilli, Vamsi SriKrishna Ghatta, Asish Krishna Sabari, Gowshith et al.

Source: Grenze International Journal of Engineering & Technology (GIJET); Jan2025, Vol. 11 Issue Part1, p819-827, 9p

FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder.

Authors: Elsayed, Ghada Abass, Eman S.

Source: Bulletin of the National Research Centre. 12/23/2024, Vol. 48 Issue 1, p1-16. 16p.

Circuit realization and FPGA-based implementation of a fractional-order chaotic system for cancellable face recognition.

Authors: Badr, Iman S. Radwan, Ahmed G. EL-Rabaie, El-Sayed M. et al.

Source: Multimedia Tools & Applications. Oct2024, Vol. 83 Issue 34, p81565-81590. 26p.

Subjects: Verilog (Computer hardware description language), Field programmable gate arrays, Receiver operating characteristic curves, Human facial recognition software, Image encryption, Bifurcation diagrams, Mathematical analysis

RTL Implementation for AMBA ASB APB Protocol at System on Chip Level.

Authors: Khan, Sikender Ali Pushpalatha Hruthik, T. Raja et al.

Source: Journal on Electronic & Automation Engineering; Mar2026, Vol. 5 Issue 1, p49-55, 7p

Design and implementation of a novel approximate carry look-ahead adder for low-power FIR filter applications.

Authors: Kumar, Shiva Badiganchela Reddy, Umamaheswara Galiveeti

Source: International Journal of Reconfigurable & Embedded Systems; Mar2026, Vol. 15 Issue 1, p248-258, 11p

Modelling and Analysis of Adaptive ON-Time Controlled Boost Converter Using Verilog-A.

Authors: M.S., Sunita Gowda, Praphul Lakshman, Shreya et al.

Source: Australian Journal of Electrical & Electronic Engineering. Sep2025, Vol. 22 Issue 3, p397-409. 13p.

Subjects: Verilog (Computer hardware description language), DC-to-DC converters, Feedback control systems, Dynamic models, Metal oxide semiconductor field-effect transistors, Mathematical models, Simulation methods & models, Electronic design automation

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm.

Authors: Wu, Caiyun Zhang, Kai Zhang, Xin

Source: Energies (19961073). Apr2024, Vol. 17 Issue 8, p1870. 18p.

Subjects: Verilog (Computer hardware description language), Search algorithms, Closed loop systems, Beetles, Gate array circuits

Content addressable memory (CAM) based robust anonymous authentication and integrity preservation scheme for wireless body area networks (WBAN).

Authors: Rajasekaran, Arun Sekar Azees, M. Dash, Chandra Sekhar et al.

Source: Multimedia Tools & Applications. Feb2024, Vol. 83 Issue 7, p20429-20455. 27p.

Subjects: Verilog (Computer hardware description language), Elliptic curve cryptography, Artificial implants, Software development tools, Body area networks

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation.

Authors: Rajasekaran, Arun Sekar Azees, M.

Source: International Journal of Information Security. Feb2024, Vol. 23 Issue 1, p1-13. 13p.

Subjects: Body area networks, Verilog (Computer hardware description language), Field programmable gate arrays, Computer hardware description languages, Privacy

A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.

Authors: Basha, Mudasar Siva Kumar, Munuswamy Chinnaiah, Mangali Chinna et al.

Source: Sensors (14248220). May2024, Vol. 24 Issue 9, p2775. 22p.

An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.

Authors: Kumar, Sujeet Ray, Kailash Chandra

Source: International Journal of Parallel, Emergent & Distributed Systems; Jan2026, Vol. 41 Issue 1, p89-103, 15p