A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware.
Saved in:
| Title: | A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware. |
|---|---|
| Authors: | Nedjah, Nadia1, nadia@pq.cnpq.br, Macedo Mourelle, Luiza2, ldmm@eng.uerj.br, Wang, Chao3, cswang@ustc.edu.cn |
| Source: | International Journal of Parallel Programming; Dec2016, Vol. 44 Issue 6, p1102-1117, 16p |
| Database: | Applied Science & Technology Source |
| ISSN: | 08857458 |
|---|---|
| DOI: | 10.1007/s10766-016-0408-7 |
