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Design Methodology for Voltage-Scaled Clock Distribution Networks.

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Bibliographic Details
Title: Design Methodology for Voltage-Scaled Clock Distribution Networks.
Authors: Sitik, Can1, Liu, Weicheng2, Taskin, Baris1, Salman, Emre2
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2016, Vol. 24 Issue 10, p3080-3093, 14p
Database: Applied Science & Technology Source
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  Availability: 0
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DbLabel: Applied Science & Technology Source
An: 118364323
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/TVLSI.2016.2539926
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      – Code: eng
        Text: English
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        PageCount: 14
        StartPage: 3080
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      – TitleFull: Design Methodology for Voltage-Scaled Clock Distribution Networks.
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            NameFull: Sitik, Can
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            NameFull: Liu, Weicheng
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            NameFull: Taskin, Baris
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            NameFull: Salman, Emre
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              Text: Oct2016
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              Y: 2016
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              Value: 24
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              Value: 10
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