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SLECTS: Slew-Driven Clock Tree Synthesis.

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Title: SLECTS: Slew-Driven Clock Tree Synthesis.
Authors: Liu, Weicheng1, Sitik, Can2, Salman, Emre1, emre.salman@stonybrook.edu, Taskin, Baris2, Sundareswaran, Savithri3, Huang, Benjamin3
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Apr2019, Vol. 27 Issue 4, p864-874, 11p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 135535768
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/TVLSI.2018.2888958
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      – Code: eng
        Text: English
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      – TitleFull: SLECTS: Slew-Driven Clock Tree Synthesis.
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            NameFull: Liu, Weicheng
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            NameFull: Sitik, Can
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            NameFull: Salman, Emre
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            NameFull: Taskin, Baris
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            NameFull: Sundareswaran, Savithri
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            NameFull: Huang, Benjamin
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              Text: Apr2019
              Type: published
              Y: 2019
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