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Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors.

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Title: Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors.
Authors: Singh, Ajay Kumar1, ajay.singh@mmu.edu.my, Tan Chun Fui1, Tan Wee Xin Wilson1
Source: International Journal of Electrical & Computer Engineering (2088-8708); Jun2020 (Part I), Vol. 10 Issue 3, p1764-1771, 8p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 141042830
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.11591/ijece.v10i2.pp1764-1771
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      – Code: eng
        Text: English
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        PageCount: 8
        StartPage: 1764
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      – TitleFull: Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors.
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            NameFull: Singh, Ajay Kumar
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            NameFull: Tan Chun Fui
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            NameFull: Tan Wee Xin Wilson
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            – D: 01
              M: 06
              Text: Jun2020 (Part I)
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              Y: 2020
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            – TitleFull: International Journal of Electrical & Computer Engineering (2088-8708)
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