APA (7th ed.) Citation

Vikram, A., Agarwal, V., & Agarwal, A. (2020). CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication. IETE Journal of Research, 66(5), 677. https://doi.org/10.1080/03772063.2018.1517617

Chicago Style (17th ed.) Citation

Vikram, Abhishek, Vineeta Agarwal, and Anshul Agarwal. "CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication." IETE Journal of Research 66, no. 5 (2020): 677. https://doi.org/10.1080/03772063.2018.1517617.

MLA (9th ed.) Citation

Vikram, Abhishek, et al. "CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication." IETE Journal of Research, vol. 66, no. 5, 2020, p. 677, https://doi.org/10.1080/03772063.2018.1517617.