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CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.

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Title: CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.
Authors: Vikram, Abhishek1, abvikram@ieee.org, Agarwal, Vineeta1, vineeta@mnnit.ac.in, Agarwal, Anshul2, anshul@nitdelhi.ac.in
Source: IETE Journal of Research; Sep-Oct2020, Vol. 66 Issue 5, p677-684, 8p
Database: Applied Science & Technology Source
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Header DbId: aci
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        Value: 10.1080/03772063.2018.1517617
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      – Code: eng
        Text: English
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        PageCount: 8
        StartPage: 677
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      – TitleFull: CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.
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            NameFull: Vikram, Abhishek
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            – D: 01
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              Text: Sep-Oct2020
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