CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication.
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| Title: | CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication. |
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| Authors: | Vikram, Abhishek1, abvikram@ieee.org, Agarwal, Vineeta1, vineeta@mnnit.ac.in, Agarwal, Anshul2, anshul@nitdelhi.ac.in |
| Source: | IETE Journal of Research; Sep-Oct2020, Vol. 66 Issue 5, p677-684, 8p |
| Database: | Applied Science & Technology Source |
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