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Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core.

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Title: Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core.
Authors: Barbirotta, Marcello1, marcello.barbirotta@uniroma1.it, Cheikh, Abdallah1, Mastrandrea, Antonio1, Menichelli, Francesco1, Ottavi, Marco2,3, Olivieri, Mauro1, marcello.barbirotta@uniroma1.it
Source: Journal of Low Power Electronics & Applications; Mar2023, Vol. 13 Issue 1, p2, 13p
Database: Applied Science & Technology Source
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  Data: Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core.
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        Value: 10.3390/jlpea13010002
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      – Code: eng
        Text: English
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        PageCount: 13
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      – TitleFull: Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core.
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              Text: Mar2023
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              Y: 2023
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