APA (7th ed.) Citation

Paris, P. C. D., & Pedrino, E. C. (2025). A high-level simulator for Network-on-Chip. Integrated Computer-Aided Engineering, 32(1), 55. https://doi.org/10.3233/ICA-240743

Chicago Style (17th ed.) Citation

Paris, Paulo Cesar Donizeti, and Emerson Carlos Pedrino. "A High-level Simulator for Network-on-Chip." Integrated Computer-Aided Engineering 32, no. 1 (2025): 55. https://doi.org/10.3233/ICA-240743.

MLA (9th ed.) Citation

Paris, Paulo Cesar Donizeti, and Emerson Carlos Pedrino. "A High-level Simulator for Network-on-Chip." Integrated Computer-Aided Engineering, vol. 32, no. 1, 2025, p. 55, https://doi.org/10.3233/ICA-240743.