View in EDS

A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay.

Saved in:
Bibliographic Details
Title: A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay.
Authors: Sharma, Buddhi Prakash1, p20200414@pilani.bits-pilani.ac.in, Rajagopal, Rajeev1, f20201237@pilani.bits-pilani.ac.in, Sekhar, Ranjeeth1, f20200316@pilani.bits-pilani.ac.in, Gupta, Anu1, anug@pilani.bits-pilani.ac.in, Shekhar, Chandra1, chandra.shekhar@pilani.bits-pilani.ac.in
Source: Journal of Circuits, Systems & Computers; 1/30/2025, Vol. 34 Issue 2, p1-24, 24p
Database: Applied Science & Technology Source
FullText Text:
  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 182884203
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AU" term="%22Sharma%2C+Buddhi+Prakash%22">Sharma, Buddhi Prakash</searchLink><relatesTo>1</relatesTo>, <i>p20200414@pilani.bits-pilani.ac.in</i><br /><searchLink fieldCode="AU" term="%22Rajagopal%2C+Rajeev%22">Rajagopal, Rajeev</searchLink><relatesTo>1</relatesTo>, <i>f20201237@pilani.bits-pilani.ac.in</i><br /><searchLink fieldCode="AU" term="%22Sekhar%2C+Ranjeeth%22">Sekhar, Ranjeeth</searchLink><relatesTo>1</relatesTo>, <i>f20200316@pilani.bits-pilani.ac.in</i><br /><searchLink fieldCode="AU" term="%22Gupta%2C+Anu%22">Gupta, Anu</searchLink><relatesTo>1</relatesTo>, <i>anug@pilani.bits-pilani.ac.in</i><br /><searchLink fieldCode="AU" term="%22Shekhar%2C+Chandra%22">Shekhar, Chandra</searchLink><relatesTo>1</relatesTo>, <i>chandra.shekhar@pilani.bits-pilani.ac.in</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>; 1/30/2025, Vol. 34 Issue 2, p1-24, 24p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=182884203
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1142/S021812662550063X
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 24
        StartPage: 1
    Titles:
      – TitleFull: A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Sharma, Buddhi Prakash
      – PersonEntity:
          Name:
            NameFull: Rajagopal, Rajeev
      – PersonEntity:
          Name:
            NameFull: Sekhar, Ranjeeth
      – PersonEntity:
          Name:
            NameFull: Gupta, Anu
      – PersonEntity:
          Name:
            NameFull: Shekhar, Chandra
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 30
              M: 01
              Text: 1/30/2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 02181266
          Numbering:
            – Type: volume
              Value: 34
            – Type: issue
              Value: 2
          Titles:
            – TitleFull: Journal of Circuits, Systems & Computers
              Type: main
ResultId 1