APA (7th ed.) Citation

Li, C., Hu, H., Chen, Y., & Lin, S. (2025). Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier. International Journal of Circuit Theory & Applications, 53(4), 2409. https://doi.org/10.1002/cta.4207

Chicago Style (17th ed.) Citation

Li, Chung‐Yi, Hong‐Chi Hu, Yuan‐Ho Chen, and Shinn‐Yn Lin. "Low‐latency and Power‐efficient Row‐based Binary‐weighted Compensator for Fixed‐width Booth Multiplier." International Journal of Circuit Theory & Applications 53, no. 4 (2025): 2409. https://doi.org/10.1002/cta.4207.

MLA (9th ed.) Citation

Li, Chung‐Yi, et al. "Low‐latency and Power‐efficient Row‐based Binary‐weighted Compensator for Fixed‐width Booth Multiplier." International Journal of Circuit Theory & Applications, vol. 53, no. 4, 2025, p. 2409, https://doi.org/10.1002/cta.4207.