View in EDS

Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier.

Saved in:
Bibliographic Details
Title: Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier.
Authors: Li, Chung‐Yi1,2, Hu, Hong‐Chi3, Chen, Yuan‐Ho2,3, chenyh@mail.cgu.edu.tw, Lin, Shinn‐Yn2
Source: International Journal of Circuit Theory & Applications; Apr2025, Vol. 53 Issue 4, p2409-2426, 18p
Database: Applied Science & Technology Source
FullText Text:
  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 184198899
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AU" term="%22Li%2C+Chung‐Yi%22">Li, Chung‐Yi</searchLink><relatesTo>1,2</relatesTo><br /><searchLink fieldCode="AU" term="%22Hu%2C+Hong‐Chi%22">Hu, Hong‐Chi</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AU" term="%22Chen%2C+Yuan‐Ho%22">Chen, Yuan‐Ho</searchLink><relatesTo>2,3</relatesTo>, <i>chenyh@mail.cgu.edu.tw</i><br /><searchLink fieldCode="AU" term="%22Lin%2C+Shinn‐Yn%22">Lin, Shinn‐Yn</searchLink><relatesTo>2</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Circuit+Theory+%26+Applications%22">International Journal of Circuit Theory & Applications</searchLink>; Apr2025, Vol. 53 Issue 4, p2409-2426, 18p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=184198899
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1002/cta.4207
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 18
        StartPage: 2409
    Titles:
      – TitleFull: Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Li, Chung‐Yi
      – PersonEntity:
          Name:
            NameFull: Hu, Hong‐Chi
      – PersonEntity:
          Name:
            NameFull: Chen, Yuan‐Ho
      – PersonEntity:
          Name:
            NameFull: Lin, Shinn‐Yn
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 04
              Text: Apr2025
              Type: published
              Y: 2025
          Identifiers:
            – Type: issn-print
              Value: 00989886
          Numbering:
            – Type: volume
              Value: 53
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: International Journal of Circuit Theory & Applications
              Type: main
ResultId 1