Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier.
Saved in:
| Title: | Low‐latency and power‐efficient row‐based binary‐weighted compensator for fixed‐width Booth multiplier. |
|---|---|
| Authors: | Li, Chung‐Yi1,2, Hu, Hong‐Chi3, Chen, Yuan‐Ho2,3, chenyh@mail.cgu.edu.tw, Lin, Shinn‐Yn2 |
| Source: | International Journal of Circuit Theory & Applications; Apr2025, Vol. 53 Issue 4, p2409-2426, 18p |
| Database: | Applied Science & Technology Source |
Be the first to leave a comment!
