APA (7th ed.) Citation

PRAKASH, V. N. V. S., KUMAR, B. U., SREE, S. S., SUNEEL, E., CHARAN, C. S., & T, R. (2025). Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs. Journal of Active & Passive Electronic Devices, 19(1), 53.

Chicago Style (17th ed.) Citation

PRAKASH, V. N. V. SATYA, B. UDAY KUMAR, S. SOWMYA SREE, E. SUNEEL, C. SAI CHARAN, and RAMASWAMY T. "Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs." Journal of Active & Passive Electronic Devices 19, no. 1 (2025): 53.

MLA (9th ed.) Citation

PRAKASH, V. N. V. SATYA, et al. "Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs." Journal of Active & Passive Electronic Devices, vol. 19, no. 1, 2025, p. 53.