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Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs.

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Title: Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs.
Authors: PRAKASH, V. N. V. SATYA1, ramaswamy.t@sreenidhi.edu.in, KUMAR, B. UDAY1, SREE, S. SOWMYA1, SUNEEL, E.1, CHARAN, C. SAI1, RAMASWAMY T.2
Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 1, p53-65, 13p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 188146920
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PubType: Academic Journal
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Active+%26+Passive+Electronic+Devices%22">Journal of Active & Passive Electronic Devices</searchLink>; 2025, Vol. 19 Issue 1, p53-65, 13p
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      – Code: eng
        Text: English
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        PageCount: 13
        StartPage: 53
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      – TitleFull: Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs.
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            NameFull: KUMAR, B. UDAY
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              M: 07
              Text: 2025
              Type: published
              Y: 2025
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