Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs.
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| Title: | Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs. |
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| Authors: | PRAKASH, V. N. V. SATYA1, ramaswamy.t@sreenidhi.edu.in, KUMAR, B. UDAY1, SREE, S. SOWMYA1, SUNEEL, E.1, CHARAN, C. SAI1, RAMASWAMY T.2 |
| Source: | Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 1, p53-65, 13p |
| Database: | Applied Science & Technology Source |
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