APA (7th ed.) Citation

Kavya, C. H., & Varadarajan, S. (2025). Pipelined Diagonal Matrix Codes for Error Correction in Embedded Memories. Engineering, Technology & Applied Science Research, 15(5), 28201. https://doi.org/10.48084/etasr.12069

Chicago Style (17th ed.) Citation

Kavya, C. H., and S. Varadarajan. "Pipelined Diagonal Matrix Codes for Error Correction in Embedded Memories." Engineering, Technology & Applied Science Research 15, no. 5 (2025): 28201. https://doi.org/10.48084/etasr.12069.

MLA (9th ed.) Citation

Kavya, C. H., and S. Varadarajan. "Pipelined Diagonal Matrix Codes for Error Correction in Embedded Memories." Engineering, Technology & Applied Science Research, vol. 15, no. 5, 2025, p. 28201, https://doi.org/10.48084/etasr.12069.