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Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.

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Title: Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.
Authors: PRASAD, T. JAYACHANDRA1, CHENNAKESAVULU, M.1, chennakesavuluece@rgmcet.edu.in, REDDY, BOJJ A. RAMESH2, RAO, VADDE SEETHARAMA3, HUSSAIN, SHAIK KASHIF1
Source: Journal of Active & Passive Electronic Devices; 2025, Vol. 19 Issue 4, p283-299, 17p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 191623198
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Active+%26+Passive+Electronic+Devices%22">Journal of Active & Passive Electronic Devices</searchLink>; 2025, Vol. 19 Issue 4, p283-299, 17p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=191623198
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 17
        StartPage: 283
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      – TitleFull: Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process.
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            NameFull: PRASAD, T. JAYACHANDRA
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            NameFull: CHENNAKESAVULU, M.
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            NameFull: REDDY, BOJJ A. RAMESH
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            NameFull: RAO, VADDE SEETHARAMA
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            NameFull: HUSSAIN, SHAIK KASHIF
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            – D: 01
              M: 12
              Text: 2025
              Type: published
              Y: 2025
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              Value: 19
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              Value: 4
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            – TitleFull: Journal of Active & Passive Electronic Devices
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