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[formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.

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Title: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
Authors: Shen, Shidong1,2, shensd@ios.ac.cn, Chen, Shijie1,2, chensj@ios.ac.cn, Liu, Yicheng1,2, liuyc@ios.ac.cn, Zhang, Lijun1,2, zhanglj@ios.ac.cn, Song, Fu1,2,3, songfu@ios.ac.cn, Wu, Zhilin1,2, wuzl@ios.ac.cn
Source: Journal of Systems Architecture; Jun2026, Vol. 175, pN.PAG-N.PAG, 1p
Database: Applied Science & Technology Source
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  Availability: 0
Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 193396275
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
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  Data: <searchLink fieldCode="AU" term="%22Shen%2C+Shidong%22">Shen, Shidong</searchLink><relatesTo>1,2</relatesTo>, <i>shensd@ios.ac.cn</i><br /><searchLink fieldCode="AU" term="%22Chen%2C+Shijie%22">Chen, Shijie</searchLink><relatesTo>1,2</relatesTo>, <i>chensj@ios.ac.cn</i><br /><searchLink fieldCode="AU" term="%22Liu%2C+Yicheng%22">Liu, Yicheng</searchLink><relatesTo>1,2</relatesTo>, <i>liuyc@ios.ac.cn</i><br /><searchLink fieldCode="AU" term="%22Zhang%2C+Lijun%22">Zhang, Lijun</searchLink><relatesTo>1,2</relatesTo>, <i>zhanglj@ios.ac.cn</i><br /><searchLink fieldCode="AU" term="%22Song%2C+Fu%22">Song, Fu</searchLink><relatesTo>1,2,3</relatesTo>, <i>songfu@ios.ac.cn</i><br /><searchLink fieldCode="AU" term="%22Wu%2C+Zhilin%22">Wu, Zhilin</searchLink><relatesTo>1,2</relatesTo>, <i>wuzl@ios.ac.cn</i>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Systems+Architecture%22">Journal of Systems Architecture</searchLink>; Jun2026, Vol. 175, pN.PAG-N.PAG, 1p
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=193396275
RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1016/j.sysarc.2026.103761
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      – Code: eng
        Text: English
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        PageCount: 1
        StartPage: N.PAG
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      – TitleFull: [formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.
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            NameFull: Shen, Shidong
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            NameFull: Chen, Shijie
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            NameFull: Song, Fu
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            – D: 01
              M: 06
              Text: Jun2026
              Type: published
              Y: 2026
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              Value: 175
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