AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs.
Saved in:
| Title: | AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs. |
|---|---|
| Authors: | Liang, Jiawei1,2, jliangbr@connect.ust.hk, Du, Linfeng1, linfeng.du@connect.ust.hk, Zhou, Xiaofeng1, xzhoubu@connect.ust.hk, Lin, Zhe3, linzh235@mail.sysu.edu.cn, Xu, Jiang4, jiang.xu@hkust-gz.edu.cn, Zhang, Wei1,2, wei.zhang@ust.hk |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2025, Issue 62, p1-7, 7p |
| Database: | Applied Science & Technology Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
|---|---|
| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 193986510 AccessLevel: 2 PubType: Conference PubTypeId: conference PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AU" term="%22Liang%2C+Jiawei%22">Liang, Jiawei</searchLink><relatesTo>1,2</relatesTo>, <i>jliangbr@connect.ust.hk</i><br /><searchLink fieldCode="AU" term="%22Du%2C+Linfeng%22">Du, Linfeng</searchLink><relatesTo>1</relatesTo>, <i>linfeng.du@connect.ust.hk</i><br /><searchLink fieldCode="AU" term="%22Zhou%2C+Xiaofeng%22">Zhou, Xiaofeng</searchLink><relatesTo>1</relatesTo>, <i>xzhoubu@connect.ust.hk</i><br /><searchLink fieldCode="AU" term="%22Lin%2C+Zhe%22">Lin, Zhe</searchLink><relatesTo>3</relatesTo>, <i>linzh235@mail.sysu.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Xu%2C+Jiang%22">Xu, Jiang</searchLink><relatesTo>4</relatesTo>, <i>jiang.xu@hkust-gz.edu.cn</i><br /><searchLink fieldCode="AU" term="%22Zhang%2C+Wei%22">Zhang, Wei</searchLink><relatesTo>1,2</relatesTo>, <i>wei.zhang@ust.hk</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22DAC%3A+Annual+ACM%2FIEEE+Design+Automation+Conference%22">DAC: Annual ACM/IEEE Design Automation Conference</searchLink>; 2025, Issue 62, p1-7, 7p |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=193986510 |
| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 7 StartPage: 1 Titles: – TitleFull: AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Liang, Jiawei – PersonEntity: Name: NameFull: Du, Linfeng – PersonEntity: Name: NameFull: Zhou, Xiaofeng – PersonEntity: Name: NameFull: Lin, Zhe – PersonEntity: Name: NameFull: Xu, Jiang – PersonEntity: Name: NameFull: Zhang, Wei IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: 2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 0738100X Numbering: – Type: issue Value: 62 Titles: – TitleFull: DAC: Annual ACM/IEEE Design Automation Conference Type: main |
| ResultId | 1 |