APA (7th ed.) Citation

Hatte, N. M., Kesarkar, V. V., Chirke, S. D., & Kanse, S. S. (2026). Single Cycle Risc-V Processor Using Verilog. International Scientific Journal of Engineering & Management, 5(5), 1. https://doi.org/10.55041/ISJEM07732

Chicago Style (17th ed.) Citation

Hatte, N. M., V. V. Kesarkar, S. D. Chirke, and S. S. Kanse. "Single Cycle Risc-V Processor Using Verilog." International Scientific Journal of Engineering & Management 5, no. 5 (2026): 1. https://doi.org/10.55041/ISJEM07732.

MLA (9th ed.) Citation

Hatte, N. M., et al. "Single Cycle Risc-V Processor Using Verilog." International Scientific Journal of Engineering & Management, vol. 5, no. 5, 2026, p. 1, https://doi.org/10.55041/ISJEM07732.