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Enhancing Timing-Driven FPGA Placement for Pipelined Netlists.

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Title: Enhancing Timing-Driven FPGA Placement for Pipelined Netlists.
Authors: Eguro, Ken1, eguro@ee.washington.edu, Hauck, Scott1, hauck@ee.washington.edu
Source: DAC: Annual ACM/IEEE Design Automation Conference; 2008, p34-37, 4p, 4 Diagrams, 3 Charts, 2 Graphs
Database: Applied Science & Technology Source
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PubType: Conference
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  Data: Enhancing Timing-Driven FPGA Placement for Pipelined Netlists.
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  Data: <searchLink fieldCode="AU" term="%22Eguro%2C+Ken%22">Eguro, Ken</searchLink><relatesTo>1</relatesTo>, <i>eguro@ee.washington.edu</i><br /><searchLink fieldCode="AU" term="%22Hauck%2C+Scott%22">Hauck, Scott</searchLink><relatesTo>1</relatesTo>, <i>hauck@ee.washington.edu</i>
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PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=36631543
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      – Code: eng
        Text: English
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        PageCount: 4
        StartPage: 34
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      – TitleFull: Enhancing Timing-Driven FPGA Placement for Pipelined Netlists.
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            NameFull: Eguro, Ken
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            NameFull: Hauck, Scott
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            – D: 01
              M: 02
              Text: 2008
              Type: published
              Y: 2008
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              Value: 0738100X
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            – TitleFull: DAC: Annual ACM/IEEE Design Automation Conference
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