Enhancing Timing-Driven FPGA Placement for Pipelined Netlists.
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| Title: | Enhancing Timing-Driven FPGA Placement for Pipelined Netlists. |
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| Authors: | Eguro, Ken1, eguro@ee.washington.edu, Hauck, Scott1, hauck@ee.washington.edu |
| Source: | DAC: Annual ACM/IEEE Design Automation Conference; 2008, p34-37, 4p, 4 Diagrams, 3 Charts, 2 Graphs |
| Database: | Applied Science & Technology Source |
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