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A general technique for designing totally self-checking checker for 1-out-of-N code with minimum gate delay.

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Title: A general technique for designing totally self-checking checker for 1-out-of-N code with minimum gate delay.
Authors: Tao, D. L., Hartmann, C. R. P., Lala, P. K.
Source: IEEE Transactions on Computers; July 1992, Vol. 41, p881-886, 6p
Database: Applied Science & Technology Source
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Header DbId: aci
DbLabel: Applied Science & Technology Source
An: 500010493
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: A general technique for designing totally self-checking checker for 1-out-of-N code with minimum gate delay.
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  Data: <searchLink fieldCode="AU" term="%22Tao%2C+D%2E+L%2E%22">Tao, D. L.</searchLink><br /><searchLink fieldCode="AU" term="%22Hartmann%2C+C%2E+R%2E+P%2E%22">Hartmann, C. R. P.</searchLink><br /><searchLink fieldCode="AU" term="%22Lala%2C+P%2E+K%2E%22">Lala, P. K.</searchLink>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>; July 1992, Vol. 41, p881-886, 6p
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        Value: 10.1109/12.256456
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        Text: English
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        PageCount: 6
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      – TitleFull: A general technique for designing totally self-checking checker for 1-out-of-N code with minimum gate delay.
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            NameFull: Tao, D. L.
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            NameFull: Hartmann, C. R. P.
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            NameFull: Lala, P. K.
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              Text: July 1992
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              Y: 1992
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