Design networks-on-chip with latency/ bandwidth guarantees.
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| Title: | Design networks-on-chip with latency/ bandwidth guarantees. |
|---|---|
| Authors: | Lin, S., Su, L., Su, H. |
| Source: | IET Computers & Digital Techniques; March 2009, Vol. 3 Issue 2, p184-194, 11p |
| Database: | Applied Science & Technology Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 501403491 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=501403491 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1049/iet-cdt:20080036 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 184 Titles: – TitleFull: Design networks-on-chip with latency/ bandwidth guarantees. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Lin, S. – PersonEntity: Name: NameFull: Su, L. – PersonEntity: Name: NameFull: Su, H. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: March 2009 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 17518601 Numbering: – Type: volume Value: 3 – Type: issue Value: 2 Titles: – TitleFull: IET Computers & Digital Techniques Type: main |
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