APA (7th ed.) Citation

Melouki, A., Srivastava, S., & Al-Hashimi, B. M. (2010). Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. IET Computers & Digital Techniques, 4(3), 240. https://doi.org/10.1049/iet-cdt.2008.0146

Chicago Style (17th ed.) Citation

Melouki, A., S. Srivastava, and B. M. Al-Hashimi. "Fault-tolerance Techniques for Hybrid CMOS/nanoarchitecture." IET Computers & Digital Techniques 4, no. 3 (2010): 240. https://doi.org/10.1049/iet-cdt.2008.0146.

MLA (9th ed.) Citation

Melouki, A., et al. "Fault-tolerance Techniques for Hybrid CMOS/nanoarchitecture." IET Computers & Digital Techniques, vol. 4, no. 3, 2010, p. 240, https://doi.org/10.1049/iet-cdt.2008.0146.