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Fault-tolerance techniques for hybrid CMOS/nanoarchitecture.

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Title: Fault-tolerance techniques for hybrid CMOS/nanoarchitecture.
Authors: Melouki, A., Srivastava, S., Al-Hashimi, B. M.
Source: IET Computers & Digital Techniques; May 2010, Vol. 4 Issue 3, p240-250, 11p
Database: Applied Science & Technology Source
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DbLabel: Applied Science & Technology Source
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PubType: Academic Journal
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        Value: 10.1049/iet-cdt.2008.0146
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        Text: English
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        StartPage: 240
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              Text: May 2010
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