Fault-tolerance techniques for hybrid CMOS/nanoarchitecture.
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| Title: | Fault-tolerance techniques for hybrid CMOS/nanoarchitecture. |
|---|---|
| Authors: | Melouki, A., Srivastava, S., Al-Hashimi, B. M. |
| Source: | IET Computers & Digital Techniques; May 2010, Vol. 4 Issue 3, p240-250, 11p |
| Database: | Applied Science & Technology Source |
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