APA (7th ed.) Citation

Hackenberg, D., Juckeland, G., & Brunst, H. (2012). Performance analysis of multi-level parallelism: Inter-node, intra-node and hardware accelerators. Concurrency & Computation: Practice & Experience, 24(1), 62. https://doi.org/10.1002/cpe.1725

Chicago Style (17th ed.) Citation

Hackenberg, Daniel, Guido Juckeland, and Holger Brunst. "Performance Analysis of Multi-level Parallelism: Inter-node, Intra-node and Hardware Accelerators." Concurrency & Computation: Practice & Experience 24, no. 1 (2012): 62. https://doi.org/10.1002/cpe.1725.

MLA (9th ed.) Citation

Hackenberg, Daniel, et al. "Performance Analysis of Multi-level Parallelism: Inter-node, Intra-node and Hardware Accelerators." Concurrency & Computation: Practice & Experience, vol. 24, no. 1, 2012, p. 62, https://doi.org/10.1002/cpe.1725.